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AU_LINUX_QSDK_FIG_TARGET_ALL.12.2.000.1840

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Merge AU_LINUX_QSDK_FIG_TARGET_ALL.12.2.000.1840 on remote branch

Change-Id: I71c370ff7bf0f9439824475f666bac87e5ebb1a2
Signed-off-by: Linux Build Service Account <lnxbuild@localhost>
This commit is contained in:
Linux Build Service Account 2023-03-14 23:34:04 -07:00
commit 2dad953be3
15 changed files with 352 additions and 190 deletions
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19
arch/arm/dts/ipq5332-mi01.2-qcn9160-c1.dts
View file

@ -21,24 +21,5 @@
aliases {
/delete-property/pci0;
pci2 = "/pci@10000000";
};
usb0: xhci@8a00000 {
ssphy = <1>;
};
pci2: pci@10000000 {
status = "ok";
perst_gpio = <44>;
lane = <1>;
pci_gpio {
pci_rst {
gpio = <44>;
pull = <GPIO_PULL_UP>;
oe = <GPIO_OE_ENABLE>;
drvstr = <GPIO_8MA>;
};
};
};
};

4
arch/arm/dts/ipq5332-mi03.1.dts
View file

@ -76,7 +76,6 @@
ess-switch {
switch_mac_mode0 = <PORT_WRAPPER_SGMII0_RGMII4>;
switch_mac_mode1 = <PORT_WRAPPER_SGMII0_RGMII4>;
qca8337_rst_gpio = <22>;
qca8033_gpio_cnt = <1>;
qca8033_gpio = <31>;
qca8337_switch_enable = <1>;
@ -112,6 +111,8 @@
};
qca8337_swt_info {
switch@0 {
qca8337_rst_gpio = <22>;
mac_pwr = <0xaa545>;
port_count = <3>;
update = <1>;
@ -124,6 +125,7 @@
port0_status = <0x4e>;
port6_status = <0>;
port_phy_address = <2 3 4>;
};
};
};
};

58
arch/arm/dts/ipq5332-mi04.1.dts
View file

@ -166,4 +166,62 @@
};
};
};
ess-switch {
switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
switch_mac_mode1 = <PORT_WRAPPER_SGMII_PLUS>;
qca808x_gpio = <51>;
qca808x_gpio_cnt = <1>;
napa_gpio = <22>;
qca8084_switch_enable = <1>;
port_phyinfo {
port@0 {
phy_address = <1>;
phy_type = <QCA8084_PHY_TYPE>;
uniphy_id = <0>;
uniphy_mode = <PORT_WRAPPER_SGMII_PLUS>;
};
port@1 {
phy_address = <12>;
phy_type = <QCA8081_PHY_TYPE>;
uniphy_id = <1>;
uniphy_mode = <PORT_WRAPPER_SGMII_PLUS>;
};
};
qca8084_swt_info {
switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
switch_mac_mode1 = <PORT_WRAPPER_SGMII_PLUS>;
port@0 {
phy_address = <0xff>;
phy_type = <UNUSED_PHY_TYPE>;
forced-speed = <2500>;
forced-duplex = <1>;
};
port@1 {
phy_address = <1>;
phy_type = <QCA8084_PHY_TYPE>;
};
port@2 {
phy_address = <2>;
phy_type = <QCA8084_PHY_TYPE>;
};
port@3 {
phy_address = <3>;
phy_type = <QCA8084_PHY_TYPE>;
};
port@4 {
phy_address = <0x4>;
phy_type = <QCA8084_PHY_TYPE>;
};
port@5 {
phy_address = <0xff>;
phy_type = <UNUSED_PHY_TYPE>;
forced-speed = <2500>;
forced-duplex = <1>;
};
};
};
};

3
arch/arm/dts/ipq9574-al02-c10.dts
View file

@ -22,7 +22,8 @@
/* Overriding config to support QCA8084 Switch instead of
* QCA8084 PHY
*/
qca8084_switch_enable = <1>;
qca8084_swt_port = <0>;
uniphy_force_mode = <0>;
switch_mac_mode0 = <PORT_WRAPPER_SGMII_PLUS>;
qca8084_swt_info {

2
board/qca/arm/common/cmd_bootqca.c
View file

@ -904,7 +904,7 @@ static int do_bootipq(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
}
if (ret == CMD_RET_FAILURE) {
#ifndef CONFIG_IPQ5332
#if !defined(CONFIG_IPQ5332) && !defined(CONFIG_IPQ9574)
#ifdef CONFIG_IPQ_ETH_INIT_DEFER
puts("\nNet: ");
eth_initialize();

9
board/qca/arm/ipq5332/ipq5332.c
View file

@ -1062,15 +1062,14 @@ void qca808x_phy_reset_init(void)
{
int qca808x_gpio[2] = {-1, -1}, qca808x_gpio_cnt, i;
unsigned int *qca808x_gpio_base;
uint32_t cfg;
qca808x_gpio_cnt = get_qca808x_gpio(qca808x_gpio);
if (qca808x_gpio_cnt >= 1) {
for (i = 0; i < qca808x_gpio_cnt; i++) {
if (qca808x_gpio[i] >= 0) {
qca808x_gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(qca808x_gpio[i]);
cfg = GPIO_OE | GPIO_DRV_8_MA | GPIO_PULL_UP;
writel(cfg, qca808x_gpio_base);
qca808x_gpio_base = (unsigned int *)
GPIO_CONFIG_ADDR(qca808x_gpio[i]);
writel(0x203, qca808x_gpio_base);
gpio_set_value(qca808x_gpio[i], 0x0);
}
}
@ -1097,7 +1096,7 @@ void qca808x_phy_reset_init_done(void)
qca808x_gpio_cnt = get_qca808x_gpio(qca808x_gpio);
if (qca808x_gpio_cnt >= 1) {
for (i = 0; i < qca808x_gpio_cnt; i++)
gpio_set_value(qca808x_gpio[i], 0x1);
gpio_set_value(qca808x_gpio[i], 0x3);
}
}

259
drivers/net/ipq5332/ipq5332_edma.c
View file

@ -56,6 +56,7 @@ typedef struct {
uchar ipq5332_def_enetaddr[6] = {0x00, 0x03, 0x7F, 0xBA, 0xDB, 0xAD};
phy_info_t *swt_info[QCA8084_MAX_PORTS] = {0};
ipq5332_edma_port_info_t *port_info[IPQ5332_PHY_MAX] = {0};
mdio_info_t *mdio_info[IPQ5332_PHY_MAX] = {0};
int sgmii_mode[2] = {0};
extern void ipq_phy_addr_fixup(void);
@ -77,21 +78,17 @@ extern void ipq5332_xgmac_sgmiiplus_speed_set(int port, int speed, int status);
extern void ppe_uniphy_refclk_set_25M(uint32_t uniphy_index);
extern void qca8033_phy_reset(void);
extern void ipq5332_gmac_port_disable(int port);
extern void ipq_set_mdio_mode(const int mode, const int bus);
#ifdef CONFIG_ATHRS17C_SWITCH
extern void ppe_uniphy_set_forceMode(uint32_t uniphy_index);
extern int ipq_qca8337_switch_init(ipq_s17c_swt_cfg_t *s17c_swt_cfg);
extern int ipq_qca8337_link_update(ipq_s17c_swt_cfg_t *s17c_swt_cfg);
extern void ipq_s17c_switch_reset(int gpio);
ipq_s17c_swt_cfg_t s17c_swt_cfg;
ipq_s17c_swt_cfg_t s17c_swt_cfg[IPQ5332_PHY_MAX];
#endif
static int tftp_acl_our_port;
#ifdef CONFIG_QCA8084_SWT_MODE
static int qca8084_swt_enb = 0;
static int qca8084_chip_detect = 0;
#endif /* CONFIG_QCA8084_SWT_MODE */
#ifdef CONFIG_QCA8084_BYPASS_MODE
extern void qca8084_bypass_interface_mode_set(u32 interface_mode);
extern void qca8084_phy_sgmii_mode_set(uint32_t phy_addr, u32 interface_mode);
@ -957,16 +954,18 @@ static int ipq5332_eth_init(struct eth_device *eth_dev, bd_t *this)
*/
continue;
}
/*
* set mdio mode and bus no
*/
ipq_set_mdio_mode(mdio_info[i]->mode, mdio_info[i]->bus_no);
phy_info = port_info[i]->phy_info;
if (phy_info->phy_type == UNUSED_PHY_TYPE)
continue;
#ifdef CONFIG_QCA8084_SWT_MODE
else if ((qca8084_swt_enb && qca8084_chip_detect) &&
#ifdef CONFIG_QCA8084_BYPASS_MODE
(!(qca8084_bypass_enb & i)) &&
#endif /* CONFIG_QCA8084_BYPASS_MODE */
(phy_info->phy_type == QCA8084_PHY_TYPE)) {
else if ((phy_info->phy_type == QCA8084_PHY_TYPE) &&
(priv->ops[i] == NULL)) {
printf("eth0 PHY%d ", i);
if (!ipq_qca8084_link_update(swt_info))
linkup++;
continue;
@ -974,8 +973,8 @@ static int ipq5332_eth_init(struct eth_device *eth_dev, bd_t *this)
#endif
#ifdef CONFIG_ATHRS17C_SWITCH
else if (phy_info->phy_type == ATHRS17C_SWITCH_TYPE) {
if (s17c_swt_cfg.chip_detect) {
if (!ipq_qca8337_link_update(&s17c_swt_cfg))
if (s17c_swt_cfg[i].chip_detect) {
if (!ipq_qca8337_link_update(&s17c_swt_cfg[i]))
linkup++;
continue;
}
@ -1751,6 +1750,73 @@ void ipq5332_prepare_switch_info(int offset, phy_info_t * phy_info[],
}
}
void get_mdio_info(int offset, mdio_info_t * mdio_info[], int max_phy_ports)
{
int mode;
int bus_no;
int i;
for (i = 0; i < max_phy_ports; i++)
mdio_info[i] = ipq5332_alloc_mem(sizeof(mdio_info_t));
i = 0;
for (offset = fdt_first_subnode(gd->fdt_blob, offset); offset > 0;
offset = fdt_next_subnode(gd->fdt_blob, offset)) {
mode = fdtdec_get_uint(gd->fdt_blob,
offset, "mdio_mode", 0);
bus_no = fdtdec_get_uint(gd->fdt_blob,
offset, "bus_no", 0);
mdio_info[i]->mode = mode;
mdio_info[i]->bus_no = bus_no;
++i;
}
}
#ifdef CONFIG_ATHRS17C_SWITCH
void ipq5332_prepare_qca8337_info(int phy_node, int max_phy_ports)
{
int i, s17c_rst_gpio;
for (i = 0, phy_node = fdt_first_subnode(gd->fdt_blob, phy_node);
phy_node > 0 && i < max_phy_ports; ++i,
phy_node = fdt_next_subnode(gd->fdt_blob, phy_node)) {
s17c_swt_cfg[i].chip_detect = 0;
s17c_rst_gpio = fdtdec_get_uint(gd->fdt_blob, phy_node,
"qca8337_rst_gpio", 0);
ipq_s17c_switch_reset(s17c_rst_gpio);
s17c_swt_cfg[i].update = fdtdec_get_uint(gd->fdt_blob,
phy_node, "update", 0);
s17c_swt_cfg[i].skip_vlan = fdtdec_get_uint(gd->fdt_blob,
phy_node, "skip_vlan", 0);
s17c_swt_cfg[i].pad0_mode = fdtdec_get_uint(gd->fdt_blob,
phy_node, "pad0_mode", 0);
s17c_swt_cfg[i].pad5_mode = fdtdec_get_uint(gd->fdt_blob,
phy_node, "pad5_mode", 0);
s17c_swt_cfg[i].pad6_mode = fdtdec_get_uint(gd->fdt_blob,
phy_node, "pad6_mode", 0);
s17c_swt_cfg[i].port0 = fdtdec_get_uint(gd->fdt_blob,
phy_node, "port0", 0);
s17c_swt_cfg[i].sgmii_ctrl = fdtdec_get_uint(gd->fdt_blob,
phy_node, "sgmii_ctrl", 0);
s17c_swt_cfg[i].port0_status = fdtdec_get_uint(gd->fdt_blob,
phy_node, "port0_status", 0);
s17c_swt_cfg[i].port6_status = fdtdec_get_uint(gd->fdt_blob,
phy_node, "port6_status", 0);
s17c_swt_cfg[i].port_count = fdtdec_get_uint(gd->fdt_blob,
phy_node, "port_count", 0);
s17c_swt_cfg[i].mac_pwr = fdtdec_get_uint(gd->fdt_blob,
phy_node, "mac_pwr", 0);
fdtdec_get_int_array(gd->fdt_blob, phy_node,
"port_phy_address",
s17c_swt_cfg[i].port_phy_address,
s17c_swt_cfg[i].port_count);
}
}
#endif
int ipq5332_edma_init(void *edma_board_cfg)
{
struct eth_device *dev[IPQ5332_EDMA_DEV];
@ -1763,15 +1829,15 @@ int ipq5332_edma_init(void *edma_board_cfg)
phy_info_t *phy_info;
int phy_id;
uint32_t phy_chip_id, phy_chip_id1, phy_chip_id2;
int clk[4] = {0};
int qca8084_swt_enb = 0;
int qca8084_chip_detect = 0;
#ifdef CONFIG_IPQ5332_QCA8075_PHY
static int sw_init_done = 0;
#endif
#ifdef CONFIG_QCA8084_SWT_MODE
static int qca8084_init_done = 0;
int qca8084_gpio, clk[4] = {0};
#endif
#ifdef CONFIG_ATHRS17C_SWITCH
int s17c_swt_enb = 0, s17c_rst_gpio = 0;
int s17c_swt_enb = 0;
#endif
int node, phy_addr, mode, phy_node = -1;
/*
@ -1787,12 +1853,6 @@ int ipq5332_edma_init(void *edma_board_cfg)
#endif /* CONFIG_QCA8084_BYPASS_MODE */
qca8084_swt_enb = fdtdec_get_uint(gd->fdt_blob, node,
"qca8084_switch_enable", 0);
if (qca8084_swt_enb) {
qca8084_gpio = fdtdec_get_uint(gd->fdt_blob, node,
"qca808x_gpio", 0);
if (qca8084_gpio)
ipq_qca8084_switch_hw_reset(qca8084_gpio);
}
phy_node = fdt_path_offset(gd->fdt_blob,
"/ess-switch/qca8084_swt_info");
@ -1805,44 +1865,17 @@ int ipq5332_edma_init(void *edma_board_cfg)
s17c_swt_enb = fdtdec_get_uint(gd->fdt_blob, node,
"qca8337_switch_enable", 0);
if (s17c_swt_enb) {
s17c_swt_cfg.chip_detect = 0;
s17c_rst_gpio = fdtdec_get_uint(gd->fdt_blob, node,
"qca8337_rst_gpio", 0);
ipq_s17c_switch_reset(s17c_rst_gpio);
phy_node = fdt_path_offset(gd->fdt_blob,
"/ess-switch/qca8337_swt_info");
s17c_swt_cfg.update = fdtdec_get_uint(gd->fdt_blob,
phy_node, "update", 0);
s17c_swt_cfg.skip_vlan = fdtdec_get_uint(gd->fdt_blob,
phy_node, "skip_vlan", 0);
s17c_swt_cfg.pad0_mode = fdtdec_get_uint(gd->fdt_blob,
phy_node, "pad0_mode", 0);
s17c_swt_cfg.pad5_mode = fdtdec_get_uint(gd->fdt_blob,
phy_node, "pad5_mode", 0);
s17c_swt_cfg.pad6_mode = fdtdec_get_uint(gd->fdt_blob,
phy_node, "pad6_mode", 0);
s17c_swt_cfg.port0 = fdtdec_get_uint(gd->fdt_blob,
phy_node, "port0", 0);
s17c_swt_cfg.sgmii_ctrl = fdtdec_get_uint(gd->fdt_blob,
phy_node, "sgmii_ctrl", 0);
s17c_swt_cfg.port0_status = fdtdec_get_uint(gd->fdt_blob,
phy_node, "port0_status", 0);
s17c_swt_cfg.port6_status = fdtdec_get_uint(gd->fdt_blob,
phy_node, "port6_status", 0);
s17c_swt_cfg.port_count = fdtdec_get_uint(gd->fdt_blob,
phy_node, "port_count", 0);
s17c_swt_cfg.mac_pwr = fdtdec_get_uint(gd->fdt_blob,
phy_node, "mac_pwr", 0);
fdtdec_get_int_array(gd->fdt_blob, phy_node,
"port_phy_address",
s17c_swt_cfg.port_phy_address,
s17c_swt_cfg.port_count);
ipq5332_prepare_qca8337_info(phy_node, IPQ5332_PHY_MAX);
}
#endif
phy_node = fdt_path_offset(gd->fdt_blob, "/ess-switch/port_phyinfo");
if (phy_node >= 0)
if (phy_node >= 0) {
ipq5332_prepare_port_info(phy_node, IPQ5332_PHY_MAX);
get_mdio_info(phy_node, mdio_info, IPQ5332_PHY_MAX);
}
mode = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode0", -1);
if (mode < 0) {
@ -1929,15 +1962,34 @@ int ipq5332_edma_init(void *edma_board_cfg)
if (ret)
goto init_failed;
ret = ipq5332_edma_hw_init(hw[i]);
if (ret)
goto init_failed;
/*
* setup force mode clk for QCA8084 & QCA8337
*/
clk[0] = 0x301;
clk[1] = 0x0;
clk[2] = 0x401;
clk[3] = 0x0;
for (phy_id = 0; phy_id < IPQ5332_PHY_MAX; phy_id++) {
phy_info = port_info[phy_id]->phy_info;
phy_addr = phy_info->phy_address;
ipq_set_mdio_mode(mdio_info[phy_id]->mode,
mdio_info[phy_id]->bus_no);
if(phy_info->phy_type == UNUSED_PHY_TYPE)
continue;
#ifdef CONFIG_QCA8084_SWT_MODE
if (phy_info->phy_type == QCA8084_PHY_TYPE &&
!qca8084_init_done) {
phy_addr == PORT1) {
ipq_phy_addr_fixup();
ipq_clock_init();
qca8084_init_done = 1;
}
#endif
#ifdef CONFIG_QCA8033_PHY
@ -2013,15 +2065,21 @@ int ipq5332_edma_init(void *edma_board_cfg)
#endif
#ifdef CONFIG_QCA8084_SWT_MODE
case QCA8084_PHY:
qca8084_chip_detect = 1;
#ifdef CONFIG_QCA8084_BYPASS_MODE
if (qca8084_bypass_enb &&
(phy_addr == PORT4)) {
ipq_qca8084_phy_hw_init(
&ipq5332_edma_dev[i]->ops[phy_id],
phy_addr);
}
qca8084_bypass_interface_mode_set(
PHY_SGMII_BASET);
} else
#endif /* CONFIG_QCA8084_BYPASS_MODE */
{
if (qca8084_swt_enb)
++qca8084_chip_detect;
}
break;
#endif
#ifdef CONFIG_ATHRS17C_SWITCH
@ -2031,7 +2089,18 @@ int ipq5332_edma_init(void *edma_board_cfg)
port_info[phy_id]->uniphy_id);
ppe_uniphy_refclk_set_25M(
port_info[phy_id]->uniphy_id);
s17c_swt_cfg.chip_detect = 1;
++s17c_swt_cfg[phy_id].chip_detect;
ipq5332_port_mac_clock_reset(phy_id);
/*Force Link-speed: 1000M */
ipq5332_pqsgmii_speed_set(phy_id,
0x2, 0);
ipq5332_speed_clock_set(phy_id, clk);
ret = ipq_qca8337_switch_init(
&s17c_swt_cfg[phy_id]);
if (ret < 0) {
printf("qca8337 init failed"
"_%d\n", phy_id);
}
}
break;
#endif
@ -2064,66 +2133,28 @@ int ipq5332_edma_init(void *edma_board_cfg)
}
}
ret = ipq5332_edma_hw_init(hw[i]);
for (phy_id = 0; phy_id < qca8084_chip_detect; ++phy_id) {
if (ret)
goto init_failed;
ipq_set_mdio_mode(mdio_info[phy_id]->mode,
mdio_info[phy_id]->bus_no);
#if defined(CONFIG_QCA8084_SWT_MODE) || defined(CONFIG_ATHRS17C_SWITCH)
/** QCA8084 & QCA8337 switch specific configurations */
if ((qca8084_swt_enb && qca8084_chip_detect) ||
(s17c_swt_cfg.chip_detect == 1)) {
#ifdef CONFIG_QCA8084_BYPASS_MODE
if (qca8084_bypass_enb)
qca8084_bypass_interface_mode_set(PHY_SGMII_BASET);
#endif /* CONFIG_QCA8084_BYPASS_MODE */
/*
* Force speed ipq5332 1st port
* for QCA8084 switch mode
ipq5332_port_mac_clock_reset(phy_id);
/* Force Link-speed: 2500M
* Force Link-status: enable
*/
clk[0] = 0x301;
clk[1] = 0x0;
clk[2] = 0x401;
clk[3] = 0x0;
ipq5332_xgmac_sgmiiplus_speed_set(phy_id, 0x4, 0);
pr_debug("Force speed for QCA8084 & QCA8337 "
"switch mode \n");
ipq5332_port_mac_clock_reset(PORT0);
#if defined(CONFIG_QCA8084_SWT_MODE)
if (qca8084_chip_detect) {
/** Force Link-speed: 2500M
* Force Link-status: enable */
ipq5332_xgmac_sgmiiplus_speed_set(PORT0,
0x4, 0);
} else
#endif
{
/*Force Link-speed: 1000M */
ipq5332_pqsgmii_speed_set(PORT0, 0x2, 0);
ipq5332_speed_clock_set(phy_id, clk);
ret = ipq_qca8084_hw_init(swt_info);
if (ret < 0) {
printf("qca8084 switch mode hw"
"_init failed %d\n",
phy_id);
}
ipq5332_speed_clock_set(PORT0, clk);
#if defined(CONFIG_QCA8084_SWT_MODE)
if (qca8084_chip_detect) {
ret = ipq_qca8084_hw_init(swt_info);
if (ret < 0) {
printf("Error: qca8084 switch mode"
"hw_init failed \n");
goto init_failed;
}
}
else
#endif
{
ret = ipq_qca8337_switch_init(&s17c_swt_cfg);
if (ret < 0)
goto init_failed;
}
}
#endif
eth_register(dev[i]);
}

100
drivers/net/ipq9574/ipq9574_edma.c
View file

@ -47,6 +47,7 @@ static struct ipq9574_eth_dev *ipq9574_edma_dev[IPQ9574_EDMA_DEV];
uchar ipq9574_def_enetaddr[6] = {0x00, 0x03, 0x7F, 0xBA, 0xDB, 0xAD};
phy_info_t *phy_info[IPQ9574_PHY_MAX] = {0};
phy_info_t *swt_info[QCA8084_MAX_PORTS] = {0};
mdio_info_t *mdio_info[IPQ9574_PHY_MAX] = {0};
int sgmii_mode[2] = {0};
extern void ipq_phy_addr_fixup(void);
@ -60,6 +61,7 @@ extern int ipq_qca8033_phy_init(struct phy_ops **ops, u32 phy_id);
extern int ipq_qca8081_phy_init(struct phy_ops **ops, u32 phy_id);
extern int ipq_qca_aquantia_phy_init(struct phy_ops **ops, u32 phy_id);
extern int ipq_board_fw_download(unsigned int phy_addr);
extern void ipq_set_mdio_mode(const int mode, const int bus);
#ifdef CONFIG_QCA8084_PHY_MODE
extern void ipq_qca8084_phy_hw_init(struct phy_ops **ops, u32 phy_addr);
@ -74,7 +76,7 @@ extern void ipq_qca8084_switch_hw_reset(int gpio);
#endif /* CONFIG_QCA8084_SWT_MODE */
static int tftp_acl_our_port;
static int qca8084_swt_enb = 0;
static int qca8084_swt_port = -1;
/*
* EDMA hardware instance
@ -934,6 +936,11 @@ static int ipq9574_eth_init(struct eth_device *eth_dev, bd_t *this)
* else we will return with -1;
*/
for (i = 0; i < IPQ9574_PHY_MAX; i++) {
/*
* set mdio mode and bus no
*/
ipq_set_mdio_mode(mdio_info[i]->mode, mdio_info[i]->bus_no);
if (current_active_port != -1 && i != current_active_port) {
ipq9574_gmac_port_disable(i);
ppe_port_bridge_txmac_set(i + 1, 1);
@ -996,10 +1003,9 @@ static int ipq9574_eth_init(struct eth_device *eth_dev, bd_t *this)
return sfp_mode;
}
#ifdef CONFIG_QCA8084_SWT_MODE
} else if (qca8084_swt_enb && (phy_info[i]->phy_type == QCA8084_PHY_TYPE)) {
} else if ((qca8084_swt_port == i)&& (phy_info[i]->phy_type == QCA8084_PHY_TYPE)) {
if (!ipq_qca8084_link_update(swt_info))
linkup++;
i = PORT3;
continue;
#endif /* CONFIG_QCA8084_SWT_MODE */
} else {
@ -1308,7 +1314,7 @@ static int ipq9574_eth_init(struct eth_device *eth_dev, bd_t *this)
ipq9574_speed_clock_set(i, clk);
#ifdef CONFIG_QCA8084_PHY_MODE
if (!qca8084_swt_enb && (phy_info[i]->phy_type == QCA8084_PHY_TYPE))
if ((qca8084_swt_port != i) && (phy_info[i]->phy_type == QCA8084_PHY_TYPE))
qca8084_phy_uqxgmii_speed_fixup(phy_info[i]->phy_address,
i + 1, status, curr_speed[i]);
#endif /* CONFIG_QCA8084_PHY_MODE */
@ -1318,7 +1324,7 @@ static int ipq9574_eth_init(struct eth_device *eth_dev, bd_t *this)
if (i == aquantia_port[0] || i == aquantia_port[1] ||
i == aquantia_port[2] ||
((phy_info[i]->phy_type == QCA8084_PHY_TYPE) &&
(!qca8084_swt_enb))) {
(qca8084_swt_port != i))) {
ipq9574_uxsgmii_speed_set(i, mac_speed, duplex, status);
}
else if ((i == sfp_port[0] || i == sfp_port[1] || i == sfp_port[2]) && sgmii_fiber == 0)
@ -1911,6 +1917,27 @@ void get_phy_address(int offset, phy_info_t * phy_info[])
}
}
void get_mdio_info(int offset, mdio_info_t * mdio_info[])
{
int mode;
int bus_no;
int i;
for (i = 0; i < IPQ9574_PHY_MAX; i++)
mdio_info[i] = ipq9574_alloc_mem(sizeof(mdio_info_t));
i = 0;
for (offset = fdt_first_subnode(gd->fdt_blob, offset); offset > 0;
offset = fdt_next_subnode(gd->fdt_blob, offset)) {
mode = fdtdec_get_uint(gd->fdt_blob,
offset, "mdio_mode", 0);
bus_no = fdtdec_get_uint(gd->fdt_blob,
offset, "bus_no", 0);
mdio_info[i]->mode = mode;
mdio_info[i]->bus_no = bus_no;
++i;
}
}
int ipq9574_edma_init(void *edma_board_cfg)
{
struct eth_device *dev[IPQ9574_EDMA_DEV];
@ -1956,9 +1983,9 @@ int ipq9574_edma_init(void *edma_board_cfg)
}
#ifdef CONFIG_QCA8084_SWT_MODE
qca8084_swt_enb = fdtdec_get_uint(gd->fdt_blob, node, "qca8084_switch_enable", 0);
qca8084_swt_port = fdtdec_get_uint(gd->fdt_blob, node, "qca8084_swt_port", -1);
qca8084_gpio = fdtdec_get_uint(gd->fdt_blob, node, "qca808x_gpio", 0);
if (qca8084_swt_enb) {
if (qca8084_swt_port != -1) {
if (qca8084_gpio)
ipq_qca8084_switch_hw_reset(qca8084_gpio);
}
@ -1969,8 +1996,14 @@ int ipq9574_edma_init(void *edma_board_cfg)
#endif
phy_node = fdt_path_offset(gd->fdt_blob, "/ess-switch/port_phyinfo");
if (phy_node >= 0)
if (phy_node >= 0) {
get_phy_address(phy_node, phy_info);
}
phy_node = fdt_path_offset(gd->fdt_blob, "/ess-switch/port_phyinfo");
if (phy_node >= 0) {
get_mdio_info(phy_node, mdio_info);
}
mode = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode0", -1);
if (mode < 0) {
@ -2069,6 +2102,13 @@ int ipq9574_edma_init(void *edma_board_cfg)
goto init_failed;
for (phy_id = 0; phy_id < IPQ9574_PHY_MAX; phy_id++) {
ipq_set_mdio_mode(mdio_info[phy_id]->mode,
mdio_info[phy_id]->bus_no);
if(phy_info[phy_id]->phy_type == UNUSED_PHY_TYPE)
continue;
if (phy_node >= 0) {
phy_addr = phy_info[phy_id]->phy_address;
#ifdef CONFIG_QCA8084_PHY
@ -2079,10 +2119,14 @@ int ipq9574_edma_init(void *edma_board_cfg)
goto init_failed;
}
#ifdef CONFIG_QCA8084_PHY
if (phy_type == QCA8084_PHY_TYPE && !qca8084_init_done) {
ipq_phy_addr_fixup();
ipq_clock_init();
qca8084_init_done = 1;
if (phy_type == QCA8084_PHY_TYPE) {
if ((qca8084_swt_port == phy_id) ||
!qca8084_init_done) {
ipq_phy_addr_fixup();
ipq_clock_init();
if (qca8084_swt_port != phy_id)
qca8084_init_done = 1;
}
}
#endif
@ -2130,7 +2174,8 @@ int ipq9574_edma_init(void *edma_board_cfg)
#endif
#ifdef CONFIG_QCA8084_PHY_MODE
case QCA8084_PHY:
ipq_qca8084_phy_hw_init(&ipq9574_edma_dev[i]->ops[phy_id], phy_addr);
if (qca8084_swt_port != phy_id)
ipq_qca8084_phy_hw_init(&ipq9574_edma_dev[i]->ops[phy_id], phy_addr);
break;
#endif
#ifdef CONFIG_IPQ9574_QCA_AQUANTIA_PHY
@ -2164,22 +2209,33 @@ int ipq9574_edma_init(void *edma_board_cfg)
#ifdef CONFIG_QCA8084_SWT_MODE
/** QCA8084 switch specific configurations */
if (qca8084_swt_enb) {
if (qca8084_swt_port != -1) {
ipq_set_mdio_mode(mdio_info[qca8084_swt_port]->mode,
mdio_info[qca8084_swt_port]->bus_no);
/** Force speed alder 1st port for QCA8084 switch mode */
switch (swt_info[0]->forced_speed) {
case FAL_SPEED_1000:
case FAL_SPEED_2500:
clk[0] = 0x201;
clk[1] = 0x0;
clk[2] = 0x301;
clk[3] = 0x0;
if (qca8084_swt_port == 4) {
clk[0] = 0x401;
clk[1] = 0x0;
clk[2] = 0x501;
clk[3] = 0x0;
} else {
clk[0] = 0x201;
clk[1] = 0x0;
clk[2] = 0x301;
clk[3] = 0x0;
}
pr_debug("Force speed Alder 1st PORT for QCA8084 switch mode \n");
ipq9574_speed_clock_set(PORT0, clk);
ipq9574_speed_clock_set(
qca8084_swt_port, clk);
/** Force Link-speed: 1000M
* Force Link-status: enable */
ipq9574_pqsgmii_speed_set(PORT0, 0x2, 0x0);
ipq9574_pqsgmii_speed_set(
qca8084_swt_port,
0x2, 0x0);
break;
default:
@ -2190,7 +2246,7 @@ int ipq9574_edma_init(void *edma_board_cfg)
ret = ipq_qca8084_hw_init(swt_info);
if (ret < 0) {
printf("Error: ipq_qca8084_hw_init failed \n");
goto init_failed;
qca8084_swt_port = -1;
}
}
#endif

8
drivers/net/ipq9574/ipq9574_ppe.c
View file

@ -32,6 +32,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define pr_info(fmt, args...) printf(fmt, ##args);
int uniphy_force_mode;
extern int is_uniphy_enabled(int uniphy_index);
extern void uniphy_port5_clock_source_set(void);
@ -475,6 +477,9 @@ void ipq9574_uxsgmii_speed_set(int port, int speed, int duplex,
switch(port) {
case 0:
case 1:
case 2:
case 3:
uniphy_index = PPE_UNIPHY_INSTANCE0;
break;
case 4:
@ -1009,6 +1014,9 @@ void ipq9574_ppe_interface_mode_init(void)
return;
}
uniphy_force_mode = fdtdec_get_uint(gd->fdt_blob, node,
"uniphy_force_mode", -1);
ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE0, mode0);
ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE1, mode1);
ppe_uniphy_mode_set(PPE_UNIPHY_INSTANCE2, mode2);

26
drivers/net/ipq9574/ipq9574_uniphy.c
View file

@ -27,6 +27,8 @@
#include <fdtdec.h>
#include "ipq_phy.h"
extern int uniphy_force_mode;
extern int is_uniphy_enabled(int uniphy_index);
DECLARE_GLOBAL_DATA_PTR;
@ -235,29 +237,35 @@ static void ppe_uniphy_qsgmii_mode_set(uint32_t uniphy_index)
mdelay(100);
}
void ppe_uniphy_set_forceMode(void)
void ppe_uniphy_set_forceMode(uint32_t uniphy_index)
{
uint32_t reg_value;
reg_value = readl(PPE_UNIPHY_BASE + UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4);
reg_value = readl(PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4);
reg_value |= UNIPHY_FORCE_SPEED_25M;
writel(reg_value, PPE_UNIPHY_BASE + UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4);
writel(reg_value, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4);
}
static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t mode)
{
if (uniphy_index == 0) {
writel(UNIPHY_MISC_SRC_PHY_MODE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC_SOURCE_SELECTION_REG_OFFSET);
writel(UNIPHY_MISC_SRC_PHY_MODE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) +
UNIPHY_MISC_SOURCE_SELECTION_REG_OFFSET);
ppe_uniphy_set_forceMode();
if (uniphy_force_mode == uniphy_index)
ppe_uniphy_set_forceMode(uniphy_index);
if (mode == EPORT_WRAPPER_SGMII_PLUS) {
writel(UNIPHY_MISC2_REG_SGMII_PLUS_MODE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET);
(uniphy_index * PPE_UNIPHY_REG_INC) +
UNIPHY_MISC2_REG_OFFSET);
} else {
writel(UNIPHY_MISC2_REG_SGMII_MODE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET);
(uniphy_index * PPE_UNIPHY_REG_INC) +
UNIPHY_MISC2_REG_OFFSET);
}
writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE +

9
drivers/net/ipq_common/ipq_qca8084.c
View file

@ -1344,6 +1344,7 @@ int ipq_qca8084_link_update(phy_info_t * phy_info[])
struct port_phy_status phy_status = {0};
int rv, port_id, status = 1;
printf("QCA8084-switch status:\n");
for (int i=PORT1; i<PORT5; i++) {
port_id = phy_info[i]->phy_address;
if (phy_info[i]->phy_type == UNUSED_PHY_TYPE)
@ -1356,7 +1357,7 @@ int ipq_qca8084_link_update(phy_info_t * phy_info[])
return status;
}
printf("QCA8084-switch PORT%d %s Speed :%d %s duplex\n", port_id,
printf("PORT%d %s Speed :%d %s duplex\n", port_id,
(phy_status.link_status?"Up":"Down"),
phy_status.speed, (phy_status.duplex?"Full":"Half"));
@ -1389,7 +1390,7 @@ int ipq_qca8084_hw_init(phy_info_t * phy_info[])
int ret = 0;
int mode0 = -1, mode1 = -1, node = -1;
qca8084_work_mode_t work_mode;
u32 port_bmp = 0x3e, cpu_bmp = 0x1;
u32 port_bmp, cpu_bmp;
int chip_type = chip_ver_get();
@ -1411,6 +1412,10 @@ int ipq_qca8084_hw_init(phy_info_t * phy_info[])
return mode1;
}
port_bmp = fdtdec_get_uint(gd->fdt_blob, node, "switch_lan_bmp", 0x3e);
cpu_bmp = fdtdec_get_uint(gd->fdt_blob, node, "switch_cpu_bmp", 0x1);
ipq_qca8084_switch_reset();
ret = ipq_qca8084_work_mode_init(mode0, mode1);

28
drivers/net/ipq_common/ipq_qca8084_clk.c
View file

@ -1220,7 +1220,6 @@ void qca8084_gcc_clock_init(qca8084_work_mode_t clk_mode, u32 pbmp)
uint32_t qca8084_port_id = 0;
/* clock type mask value for 6 manhattan ports */
uint8_t clk_mask[PORT5 + 1] = {0};
static uint8_t gcc_common_clk_init = 0;
uint8_t switch_flag = 0;
qca8084_clk_parent_t uniphy_index = QCA8084_P_UNIPHY0_RX;
@ -1267,22 +1266,19 @@ void qca8084_gcc_clock_init(qca8084_work_mode_t clk_mode, u32 pbmp)
return;
}
if (!gcc_common_clk_init) {
qca8084_gcc_common_clk_parent_enable(clk_mode);
gcc_common_clk_init = 1;
qca8084_gcc_common_clk_parent_enable(clk_mode);
/* Initialize the uniphy raw clock, if the port4 is in bypass mode, the uniphy0
* raw clock need to be dynamically updated between UQXGMII_SPEED_2500M_CLK and
* UQXGMII_SPEED_1000M_CLK according to the realtime link speed.
*/
uniphy_index = QCA8084_P_UNIPHY0_RX;
while (uniphy_index <= QCA8084_P_UNIPHY1_TX) {
/* the uniphy raw clock may be already initialized. */
if (0 == qca8084_uniphy_raw_clock_get(uniphy_index))
qca8084_uniphy_raw_clock_set(uniphy_index,
UQXGMII_SPEED_2500M_CLK);
uniphy_index++;
}
/* Initialize the uniphy raw clock, if the port4 is in bypass mode, the uniphy0
* raw clock need to be dynamically updated between UQXGMII_SPEED_2500M_CLK and
* UQXGMII_SPEED_1000M_CLK according to the realtime link speed.
*/
uniphy_index = QCA8084_P_UNIPHY0_RX;
while (uniphy_index <= QCA8084_P_UNIPHY1_TX) {
/* the uniphy raw clock may be already initialized. */
if (0 == qca8084_uniphy_raw_clock_get(uniphy_index))
qca8084_uniphy_raw_clock_set(uniphy_index,
UQXGMII_SPEED_2500M_CLK);
uniphy_index++;
}
qca8084_port_id = 0;

7
include/configs/ipq5332.h
View file

@ -452,4 +452,11 @@ extern loff_t board_env_size;
/* Flash Protect */
#define CONFIG_FLASH_PROTECT
#define CONFIG_BITBANGMII
#ifdef CONFIG_BITBANGMII
#define CONFIG_IPQ_QTI_BIT_BANGMII
#define GPIO_IN_OUT_BIT 9
#define CONFIG_BITBANGMII_MULTI
#endif
#endif /* _IPQ5332_H */

7
include/configs/ipq9574.h
View file

@ -402,4 +402,11 @@ extern loff_t board_env_size;
#undef CONFIG_BOOTM_RTEMS
#undef CONFIG_BOOTM_VXWORKS
#define CONFIG_BITBANGMII
#ifdef CONFIG_BITBANGMII
#define CONFIG_IPQ_QTI_BIT_BANGMII
#define GPIO_IN_OUT_BIT 9
#define CONFIG_BITBANGMII_MULTI
#endif
#endif /* _IPQ9574_H */

3
include/dt-bindings/qcom/eth-ipq5332.h
View file

@ -51,3 +51,6 @@
#define UNUSED_PHY_TYPE 0xFF
#endif
/* MDIO config */
#define MDIO_MODE_DEFAULT 0
#define MDIO_MODE_BITBANG 1