These changes update config as like below.
1.Config 100M, 1G as GMAC, 2.5G as XGMAC
2.Config MHT as XGMAC.
Change-Id: I0566f3a3d364931e8c8173c3604160f24c2439be
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This patch enables support for USB 2.0 in AP-MI01.2
Change-Id: I4f848a403f3aae45a9f1cfa136781fbc7a37c35a
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
The pcie AUX clock source changed to XO as per
GCC frequency plan
Change-Id: If032831d3a9523ec214a62cbed2950ee5839920e
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
Added QCN92xx's SoC global reset and MHI reset in the fuse blow path.
So, the fuse blow can be retried after any failed attempts.
Added ANTI ROLLBACK fuse read.
Change-Id: Ibf255390ffc2086fcbfa9041dc0bcb612f8d9a4e
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
These are used in multiple places so update them to use a shared #define.
Change-Id: I3cc304f04c56c9d1a22df46e68f601b5acd2b34e
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
This tool always verifies the default configuration. It is useful to be
able to verify a specific one. Add a command-line flag for this and plumb
the logic through.
Change-Id: I6022af77965aa107e4693119ac1a0ab750d3fe24
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
At present bootm_host_load_images() is passed the configuration that has
been verified, but ignores it and just uses the default configuration.
This may not be the same.
Update this function to use the selected configuration.
Change-Id: I020baa9321a88348478f1acef8a89e28ec94f3e9
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
It is currently possible to use a different configuration's signature and
thus bypass the configuration check. Make sure that the configuration node
that was hashed matches the one being checked, to catch this problem.
Also add a proper function comment to fit_config_check_sig() and make it
static.
Change-Id: Ida4ccc296c95ad2b32ff87cb4b98512fcad4bb54
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
This function only returns an error message sometimes. Update it to always
return an error message if one is available. This makes it easier to see
what went wrong.
Change-Id: I3696b20cff57914ef6ff7cbca3861ba5080be15e
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
It is useful to be a little more specific about what is being
checked. Update a few messages to help with this.
Change-Id: I1318a9da01646b5fedf1d22e3119efdbd3e7a99e
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
This fixes the CVE-2016-9840. Commit imported from [1].
inftrees.c was subtracting an offset from a pointer to an array,
in order to provide a pointer that allowed indexing starting at
the offset. This is not compliant with the C standard, for which
the behavior of a pointer decremented before its allocated memory
is undefined. Per the recommendation of a security audit of the
zlib code by Trail of Bits and TrustInSoft, in support of the
Mozilla Foundation, this tiny optimization was removed, in order
to avoid the possibility of undefined behavior.
[1]: 6a043145ca
Change-Id: I816eea011f2d22b5a3f1fda8aa672b19ed284932
Signed-off-by: Mark Adler <madler@alumni.caltech.edu>
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
mi01.2-qcn9160-c1 is derived from mi01.2.
This variant disables pci0 (enables usb3.0)
and supports qcn9160 on pcie2 port.
Change-Id: Ie0e2cd7f039fab9f80788f135c80285e61b00310
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
added boot type based nand or emmc flash selection.
So machid based flash selection becomes obsolete.
Change-Id: I96fa43d31d23397fa249e02f62b905d6e4e67770
Signed-off-by: Rajkumar Ayyasamy <quic_arajkuma@quicinc.com>
For 192MHz:
GCC_SDCC1_APPS_CFG_RCGR(0x1833008) set to 0x220b
GCC_SDCC1_APPS_M(0x183300c) set to 0x0
GCC_SDCC1_APPS_N(0X1833010) set to 0x0
GCC_SDCC1_APPS_D(0x1833014) set to 0x0
Change-Id: I2715b4428e4390f0b9b0b159e984a718d6c791a3
Signed-off-by: Rajkumar Ayyasamy <quic_arajkuma@quicinc.com>
This patch updates the CONFIG_SYS_PROMPT
from "ipq5332# " to "IPQ5332# "
Change-Id: I3c42fcc4aba23c092788c028761ddc9656cd32d9
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
Updating the AL02-C7 configuration to support QCA8084 PHY
instead of QCA8075 PHY
Change-Id: Ie838d913caeb9dd933c6bd9fbdf8ee58563bdb7a
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
This patch adds support to enable flash using machid
Change-Id: I745a941d4219dc4cd29be96876710e15185ecb8f
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch adds support for new board variant AL02-C19.
This board variant consists of one internal radio,
Waikiki 5G in pci slot 0, Waikiki 6G in pci slot 2 and
SDX in pci slot 3.
Change-Id: I43e3b5890f6bd8f6d182e4c3acc540a89f9c4a34
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Bootconfig partition can have the MAGIC value 0xA3A3A1A1
if try_mode is enabled. Update the checks in smem APIs
Change-Id: I2fb71ff5812468f3f5ecd0153c35cab7d8e4bb44
Signed-off-by: Gurumoorthy Santhakumar <quic_gsanthak@quicinc.com>
