This is due to the patch upstream:
commit 886b42bf5e54098061c8bae3d5e292a8b6897401
Author: Luis R. Rodriguez <lrodriguez@atheros.com>
Date: Thu Oct 14 11:44:27 2010 -0700
ath9k_hw: remove AR9003 2.0 support
These chipsets will not hit the market, all customers will be
on >= AR9003 2.2. This shaves down the ath9k_hw size by
24161 bytes (24 KB) on my system.
Before:
$ size drivers/net/wireless/ath/ath9k/ath9k_hw.ko
text data bss dec hex filename
292328 616 1824 294768 47f70 drivers/net/wireless/ath/ath9k/ath9k_hw.ko
$ du -b drivers/net/wireless/ath/ath9k/ath9k_hw.ko
5987825 drivers/net/wireless/ath/ath9k/ath9k_hw.ko
After:
$ size drivers/net/wireless/ath/ath9k/ath9k_hw.ko
text data bss dec hex filename
277192 616 1824 279632 44450 drivers/net/wireless/ath/ath9k/ath9k_hw.ko
$ du -b drivers/net/wireless/ath/ath9k/ath9k_hw.ko
5963664 drivers/net/wireless/ath/ath9k/ath9k_hw.ko
Cc: Yixiang Li <yixiang.li@atheros.com>
Cc: Don Breslin <don.breslin@atheros.com>
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
This comes from the upstream patch:
Author: Luis R. Rodriguez <lrodriguez@atheros.com>
Date: Mon Oct 18 22:47:54 2010 -0700
ath9k_hw: Fix TX carrier leakage for IEEE compliance on AR9003 2.2
This updates the initvals for the AR9003 2.2 chipsets. The initvals
are the initial register values we use for our registers upon hardware
reset. This synchs up the initvals to match what our latest recommendation
from our systems engineering team.
The description of changes in this update:
Improves ability to support very strong Rx conditions.
Enhances DFS support for AP-mode.
Improves performance of Tx carrier leak calibration.
Adds support for Japan channel 14 Tx filtering requirements.
Improves Tx power accuracy.
Impact:
Update required to address degraded throughput at very short range.
Update required for AP-mode DFS certification.
Update required to comply to IEEE Tx carrier leak specification.
May not meet expected +/- 2 dB Tx power accuracy without update.
The most important fix here would be the TX carrier leakage required
to comply with IEEE 802.11 specifications. The group of changes have
been tested all together in one release.
References:
Osprey 2.2 header file ver #33
Checksums:
$ ./initvals -f ar9003-2p2
0x000000004a488fc7 ar9300_2p2_radio_postamble
0x0000000046cb1300 ar9300Modes_lowest_ob_db_tx_gain_table_2p2
0x00000000e912711f ar9300Modes_fast_clock_2p2
0x0000000037ac0ee8 ar9300_2p2_radio_core
0x00000000047a7700 ar9300Common_rx_gain_table_merlin_2p2
0x0000000003f783bb ar9300_2p2_mac_postamble
0x00000000301fc841 ar9300_2p2_soc_postamble
0x000000005ec8075f ar9200_merlin_2p2_radio_core
0x0000000083372ffa ar9300_2p2_baseband_postamble
0x00000000c4f59974 ar9300_2p2_baseband_core
0x00000000e20d2e72 ar9300Modes_high_power_tx_gain_table_2p2
0x000000007fd55c70 ar9300Modes_high_ob_db_tx_gain_table_2p2
0x0000000029495000 ar9300Common_rx_gain_table_2p2
0x0000000042cb1300 ar9300Modes_low_ob_db_tx_gain_table_2p2
0x00000000c4739cd6 ar9300_2p2_mac_core
0x000000003521a300 ar9300Common_wo_xlna_rx_gain_table_2p2
0x00000000a15ccf1b ar9300_2p2_soc_preamble
0x0000000029734396 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2
0x000000002d834396 ar9300PciePhy_clkreq_enable_L1_2p2
0x0000000029834396 ar9300PciePhy_clkreq_disable_L1_2p2
$ ./initvals -f ar9003-2p2 | sha1sum
0ceddb5cf66737610fb51f04cf3e9ff71870c7b4 -
Cc: stable@kernel.org
Cc: Yixiang Li <yixiang.li@atheros.com>
Cc: Don Breslin <don.breslin@atheros.com>
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
The checksum algorithm is simple. For each array it does
the XOR of all the values. This is buggy since it allows us
to swap values within the same column of an array and it would
yield identical checksums. An example where this flaw would
happen would be if we were to use a change like the following:
diff --git a/ar9003_2p2_initvals.h b/ar9003_2p2_initvals.h
index ec98ab5..0f57343 100644
--- a/ar9003_2p2_initvals.h
+++ b/ar9003_2p2_initvals.h
@@ -22,8 +22,8 @@
static const u32 ar9300_2p2_radio_postamble[][5] = {
/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
{0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31},
- {0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800},
- {0x000160b0, 0x03284f3e, 0x03284f3e, 0x05d08f20, 0x05d08f20},
+ {0x000160ac, 0xa4653c00, 0x03284f3e, 0x24652800, 0x24652800},
+ {0x000160b0, 0x03284f3e, 0xa4653c00, 0x05d08f20, 0x05d08f20},
{0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
{0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
{0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
This change would result in the same checksum for the array
ar9300_2p2_radio_postamble. To fix this we must take into consideration
the row and column for the checksum calculation. We do this by
using a prime number in addition to each row and column and
mangle this with the value of the array x,y position. This
gives us a different value for each x,y position in the array.
With these changes the above change would not be picked up by
the initvals checksum compuation.
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
initvals.c:401: warning: format ‘%016llx’ expects type ‘long long unsigned int’, but argument 2 has type ‘u64’
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Felix has sent patches to remove a bunch of chipsets we no longer
support. There was also some fixes Felix spotted. The changes
were:
commit da5747eb89eb1511dcfc1d8b32c70370616eac92
Author: Felix Fietkau <nbd@openwrt.org>
Date: Tue Jul 13 14:52:30 2010 +0200
ath9k_hw: remove initvals for hardware which was never sold
According to documentation, The following chip revisions were never sold:
- AR9280 v1.0
- AR9285 v1.0
- AR9285 v1.1
- AR9287 v1.0
Removing initvals specific to these chip revisions saves around 30k in
binary size (tested on MIPS).
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
commit ba17bc5e55ba541d2a8765fca53b6883b667ab21
Author: Felix Fietkau <nbd@openwrt.org>
Date: Fri Jul 2 00:09:49 2010 +0200
ath9k_hw: sync initvals for ar9001 and ar9002 with Atheros
This includes the following changes/fixes:
- a bugfix for stuck beacon issues
- timing changes for improved performance
- AGC setting improvements
- fixes for high temperature issues on some chips
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
This will allow us to check the checksums on the Atheros HAL
initvals and compare against what we have. The next step will
be to parse these to write them. This will let us dump data in
whatever form we want instead of writing doing silly style fixes
first and then diff'ing them.
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
This is as it went in on the AR9003 series of patches. We'll leave
the AR9003 stuff for another commit.
We test the initvals by doing:
./initvals > checksums.txt
git diff
There is no diffs :)
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
We'll be splitting up the checks by hardware family next so
we'll need access to it on other helpers.
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Going to generate checksums for these suckers. This should
also let us reprint the initvals to any format we want.
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
