Just a skeleton for now.
[mcgrof: removed trailing white space on empty lines]
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
* Register Modification for xLNA board.
* TX gain table modification for zero calibration.
* AUX chain (LNA2) sensitivity enhancement
* Modify diversity bias default setting in INI.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
This array has been introduced by commit
3b604b6cf811ba14e4c2bb3005e29bb2fba77af0
(ath9k_hw: INI changes for WoW for AR9002
chipsets) in linux, but it is not printed
from initvals.
Add it, and update ar9002_initvals.h and
checksums.txt.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
It is a dupe of 'ar9280PciePhy_clkreq_off_L1_9280', and
it is not used in ath9k. I forgot to remove it in commit
'qca-swiss-army-knife: fix build errors if ATH9K_DIR is used'
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Some initval arrays were removed from ath9k with the
upstream commit 14fec8d9baffc026beaffa2ee9e911df9d1d4ad2
(ath9k_hw: remove duplicate initvals).
Due to the missing symbols, this causes build errors
when the ATHEROS Makefile variable is not set, and
an external ATH9K_DIR is specified:
$ make clean all ATH9K_DIR=/devel/wireless-testing/drivers/net/wireless/ath/ath9k
rm -f initvals
gcc -I"/devel/wireless-testing/drivers/net/wireless/ath/ath9k" -o initvals initvals.c sha1.c
initvals.c: In function ‘ar9001_hw_print_initvals’:
initvals.c:588:2: error: ‘ar5416Bank0_9100’ undeclared (first use in this function)
initvals.c:588:2: note: each undeclared identifier is reported only once for each function it appears in
initvals.c:589:2: error: ‘ar5416BB_RfGain_9100’ undeclared (first use in this function)
initvals.c:590:2: error: ‘ar5416Bank1_9100’ undeclared (first use in this function)
initvals.c:591:2: error: ‘ar5416Bank2_9100’ undeclared (first use in this function)
initvals.c:592:2: error: ‘ar5416Bank3_9100’ undeclared (first use in this function)
initvals.c:595:2: error: ‘ar5416Bank7_9100’ undeclared (first use in this function)
initvals.c:599:2: error: ‘ar5416Bank0_9160’ undeclared (first use in this function)
initvals.c:600:2: error: ‘ar5416BB_RfGain_9160’ undeclared (first use in this function)
initvals.c:601:2: error: ‘ar5416Bank1_9160’ undeclared (first use in this function)
initvals.c:602:2: error: ‘ar5416Bank2_9160’ undeclared (first use in this function)
initvals.c:603:2: error: ‘ar5416Bank3_9160’ undeclared (first use in this function)
initvals.c:604:2: error: ‘ar5416Bank6_9160’ undeclared (first use in this function)
initvals.c:605:2: error: ‘ar5416Bank6TPC_9160’ undeclared (first use in this function)
initvals.c:606:2: error: ‘ar5416Bank7_9160’ undeclared (first use in this function)
initvals.c: In function ‘ar9002_hw_print_initvals’:
initvals.c:597:2: error: ‘ar9285PciePhy_clkreq_always_on_L1_9285’ undeclared (first use in this function)
initvals.c:598:2: error: ‘ar9285PciePhy_clkreq_off_L1_9285’ undeclared (first use in this function)
initvals.c:605:2: error: ‘ar9285PciePhy_clkreq_always_on_L1_9285_1_2’ undeclared (first use in this function)
initvals.c:606:2: error: ‘ar9285PciePhy_clkreq_off_L1_9285_1_2’ undeclared (first use in this function)
initvals.c:613:2: error: ‘ar9287PciePhy_clkreq_always_on_L1_9287_1_1’ undeclared (first use in this function)
initvals.c:614:2: error: ‘ar9287PciePhy_clkreq_off_L1_9287_1_1’ undeclared (first use in this function)
initvals.c:617:2: error: ‘ar9271Common_normal_cck_fir_coeff_9271’ undeclared (first use in this function)
initvals.c:618:2: error: ‘ar9271Common_japan_2484_cck_fir_coeff_9271’ undeclared (first use in this function)
initvals.c:619:2: error: ‘ar9271Modes_9271_1_0_only’ undeclared (first use in this function)
make: *** [initvals] Error 1
$
Add definitions for the missing arrays to avoid
these compiler errors. Also introduce two new
macros and use those for printing the arrays.
After these changes, the initvals tool builds without
errors:
$ make clean all ATH9K_DIR=/devel/wireless-testing/drivers/net/wireless/ath/ath9k
rm -f initvals
gcc -I"/devel/wireless-testing/drivers/net/wireless/ath/ath9k" -o initvals initvals.c sha1.c
$
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Due to the recent changes in AR9340 initvals,
checksums.txt needs to be updated.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
The number of the columns to be printed usually equals
with the actual columns. The only exceptions are the
Modes arrays, where the last column is not used by
ath9k.
The patch modifies the 'ath9k_get_p_columns' helper
so that can determine the correct number of columns
based on the name of the array. The the patch also
removes the 'wide' argument of various functions
because that is not necessary anymore. Additionaly,
the superfluous INI_PRINTW macro is removed as well.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
The number of the columns to be printed is computed in
two different function. Add a helper function for that
and remove the duplicated code.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
It is obsolete since the SHA1 checksums are used.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
The SLP32_MODE/INC registers have to be programmed with
values based on the ref. clock, which could be either 25MHz
or 40MHz. Incorrect values in these registers results in
TSF drift.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Now that initvals supports the AR955X family,
refresh 'checksums.txt'.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
This is required for the QCA955X initvals, because that
contain some arrays with 9 columns.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
The current code contain lots of duplication in order to
print initval arrays for different families. Refactor the
code to get rid of the duplications. This makes the code
a bit clener, and adding support for a new family will be
easier as well.
Aslo update checksums.txt because the initvals for AR9462
are printed before AR9580.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Keep the length of the macro lines under 80 character.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Add the missing ar9340, ar9462-1p0, ar9565-1p0
families to the 'verify_checksums.sh' script.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
The comment at the end of the 'ar9340_initvals.h'
header does not match with defined constant. Fix it.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
The initvals tool contain support for the
AR9565 chip, however the sha1sum values and
the actual initval arrays are not printend
when 'initvals' is called without a family
parameter.
Add the missing 'ar9565_1p0_hw_print_initvals()'
calls to fix this. Also refresh checksums.txt.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
The 'ar9331_common_rx_gain_1p2' array was a dupe
of 'ar9485_common_rx_gain_1_1'. Since commit
8a72181377 (Update
AR9485 initvals) this is no longer the case.
Because the SHA1 values of the two arrays are
different now, verify_checksum.sh complains:
$./verify_checksums.sh
ar5008 7340125997ffffe26a3bfc854c5b9dce74b86152 pass
ar9001 8a4557f6a4e5ad2b01a40ca0519940ab775572aa pass
ar9002 67813ac6decf14f5221dd3c41126f23f4d333fc4 pass
ar9003-2p2 fdcc27a4327c6bb5e82bc7ded7387e06a2c82bb0 pass
ar9330-1p1 e01b965b87c98d865b43e5febf37cb067644e56b pass
ar9330-1p2 ab7e2aa014d2a9bd5cefad261999868888fc570e fail
+1d9e632b3fdcb2db52f95dd75ff2eac31fcac0d6 ar9331_common_rx_gain_1p2
ar9485 bbe34977a5de7a913333149ff322e767b53ec9e3 pass
ar9580-1p0 cbdf2a5efad22be6694b586f8bd9c6605697cb9f pass
$
Use the INI_PRINT macro for the 'ar9331_common_rx_gain_1p2'
array and refresh the 'ar9330_1p2_initvals.h' header.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
The initvals of the AR9462 and AR9485 chips
has been updated recently, but checksums.txt
does not reflects that. Refresh it in order to
contain the actual sha1sum values.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Add support to dump base and modal eeprom header of AR9003 family
chips.
Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Enable hw PLL power save to reduce power consumption in sleep state
Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
* update dac_async_fifo
* use peak detection for 5GHz
* Fix wrong peak detector DC offset
Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Sync with the latest INI from systems and fix the version.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
* Set BB_tpc_1.enable_pd_calibrate to 0
* Set BB_cl_cal_ctrl.enable_parallel_cal to 1
* Enable "enable_dac_async_fifo" and "enable_adc_async_fifo"
to fix some dac/adc timing issue,
e.g. EVM won't degrade when setting core voltage to 1.15V.
Set BB_gen_controls.enable_dac_async_fifo=1
Set BB_gen_controls.enable_adc_async_fifo=1
* Improve LNA2 Sensitivity ~1dB
Set ch0_PLLCLKMODA2WLAN.inv_clk320_adc_ch0 = 1
* Correct alternate chain RSSI when doing diversity
Set BB_bbb_sig_detect.ant_switch_time to 63
* Refer to RACK RX gain report and modify RF gain table for LNA2
* Invert the phase of the root of both clocks
(setting flip_pllclk320 = 1) and set inv_clk320_adc back = 0.
Set ch0_PLLCLKMODA2WLAN.flip_pllclk320 to 1
Set ch0_PLLCLKMODA2WLAN.inv_clk320_adc_ch0 to 0
* Remove MAC PCU registers MAC_PCU_TSF_L32/MAC_PCU_TSF_U32.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
