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https://github.com/qca/qca-swiss-army-knife.git
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Add support for generating the AR9002 initvals from Atheros sources
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
This commit is contained in:
Felix Fietkau
Luis R. Rodriguez
parent
7f46f1715e
commit
41581499b5
2 changed files with 94 additions and 60 deletions
13
Makefile
13
Makefile
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@ -1,7 +1,16 @@
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ifdef ATHEROS
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CFLAGS += -DATHEROS
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ATHEROS_DEPS += ar9300_osprey20.ini
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ATHEROS_DEPS += ar9300_osprey22.ini
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ATHEROS_DEPS += \
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ar9280.ini \
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ar9280_merlin2.ini \
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ar9285.ini \
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ar9285_v1_2.ini \
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ar9287.ini \
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ar9287_1_1.ini \
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ar9271.ini \
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ar9300_osprey20.ini \
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ar9300_osprey22.ini
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endif
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initvals: ar5008_initvals.h ar9001_initvals.h ar9002_initvals.h ar9003_2p0_initvals.h ar9003_2p2_initvals.h $(ATHEROS_DEPS) initvals.c
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141
initvals.c
141
initvals.c
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@ -24,6 +24,80 @@ typedef uint64_t u64;
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#else
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#define ar9280Modes_merlin ar9280Modes_9280
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#define ar9280Common_merlin ar9280Common_9280
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#include "ar9280.ini"
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#define ar9280Modes_merlin2 ar9280Modes_9280_2
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#define ar9280Common_merlin2 ar9280Common_9280_2
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#define ar9280Modes_fast_clock_merlin2 ar9280Modes_fast_clock_9280_2
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#define ar9280Modes_backoff_23db_rxgain_merlin2 ar9280Modes_backoff_23db_rxgain_9280_2
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#define ar9280Modes_original_rxgain_merlin2 ar9280Modes_original_rxgain_9280_2
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#define ar9280Modes_backoff_13db_rxgain_merlin2 ar9280Modes_backoff_13db_rxgain_9280_2
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#define ar9280Modes_high_power_tx_gain_merlin2 ar9280Modes_high_power_tx_gain_9280_2
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#define ar9280Modes_original_tx_gain_merlin2 ar9280Modes_original_tx_gain_9280_2
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#define ar9280Modes_mixed_power_tx_gain_merlin2 ar9280Modes_mixed_power_tx_gain_9280_2
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#define ar9280PciePhy_clkreq_off_L1_merlin ar9280PciePhy_clkreq_off_L1_9280
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#define ar9280PciePhy_clkreq_always_on_L1_merlin ar9280PciePhy_clkreq_always_on_L1_9280
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#define ar9280PciePhy_AWOW_merlin ar9280PciePhy_AWOW_9280
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#include "ar9280_merlin2.ini"
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#define ar9285Modes_kite ar9285Modes_9285
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#define ar9285Common_kite ar9285Common_9285
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#define ar9285PciePhy_clkreq_always_on_L1_kite ar9285PciePhy_clkreq_always_on_L1_9285
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#define ar9285PciePhy_clkreq_off_L1_kite ar9285PciePhy_clkreq_off_L1_9285
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#include "ar9285.ini"
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#define ar9285Modes_kite1_2 ar9285Modes_9285_1_2
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#define ar9285Common_kite1_2 ar9285Common_9285_1_2
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#define ar9285Modes_high_power_tx_gain_kite1_2 ar9285Modes_high_power_tx_gain_9285_1_2
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#define ar9285Modes_original_tx_gain_kite1_2 ar9285Modes_original_tx_gain_9285_1_2
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#define ar9285PciePhy_clkreq_always_on_L1_kite1_2 ar9285PciePhy_clkreq_always_on_L1_9285_1_2
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#define ar9285PciePhy_clkreq_off_L1_kite1_2 ar9285PciePhy_clkreq_off_L1_9285_1_2
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#define ar9285PciePhy_AWOW_kite1_2 ar9285PciePhy_AWOW_9285_1_2
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#define ar9285Modes_Elijah2_0_normal_power ar9285Modes_XE2_0_normal_power
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#define ar9285Modes_Elijah2_0_high_power ar9285Modes_XE2_0_high_power
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#include "ar9285_v1_2.ini"
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#define ar9287Modes_kiwi1_0 ar9287Modes_9287_1_0
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#define ar9287Common_kiwi1_0 ar9287Common_9287_1_0
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#define ar9287Modes_tx_gain_kiwi1_0 ar9287Modes_tx_gain_9287_1_0
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#define ar9287Modes_rx_gain_kiwi1_0 ar9287Modes_rx_gain_9287_1_0
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#define ar9287PciePhy_clkreq_always_on_L1_kiwi1_0 ar9287PciePhy_clkreq_always_on_L1_9287_1_0
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#define ar9287PciePhy_clkreq_off_L1_kiwi1_0 ar9287PciePhy_clkreq_off_L1_9287_1_0
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#define ar9287PciePhy_AWOW_kiwi1_0 ar9287PciePhy_AWOW_9287_1_0
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#include "ar9287.ini"
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#define ar9287Modes_kiwi1_1 ar9287Modes_9287_1_1
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#define ar9287Common_kiwi1_1 ar9287Common_9287_1_1
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#define ar9287Common_normal_cck_fir_coeff_kiwi1_1 ar9287Common_normal_cck_fir_coeff_9287_1_1
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#define ar9287Common_japan_2484_cck_fir_coeff_kiwi1_1 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1
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#define ar9287Modes_tx_gain_kiwi1_1 ar9287Modes_tx_gain_9287_1_1
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#define ar9287Modes_rx_gain_kiwi1_1 ar9287Modes_rx_gain_9287_1_1
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#define ar9287PciePhy_clkreq_always_on_L1_kiwi1_1 ar9287PciePhy_clkreq_always_on_L1_9287_1_1
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#define ar9287PciePhy_clkreq_off_L1_kiwi1_1 ar9287PciePhy_clkreq_off_L1_9287_1_1
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#define ar9287PciePhy_AWOW_kiwi1_1 ar9287PciePhy_AWOW_9287_1_1
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#include "ar9287_1_1.ini"
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#define ar9271Modes_K2 ar9271Modes_9271
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#define ar9271Common_K2 ar9271Common_9271
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#define ar9271Common_normal_cck_fir_coeff_K2 ar9271Common_normal_cck_fir_coeff_9271
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#define ar9271Common_japan_2484_cck_fir_coeff_K2 ar9271Common_japan_2484_cck_fir_coeff_9271
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#define ar9271Modes_K2_1_0_only ar9271Modes_9271_1_0_only
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#define ar9271Modes_K2_ANI_reg ar9271Modes_9271_ANI_reg
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#define ar9271Modes_normal_power_tx_gain_K2 ar9271Modes_normal_power_tx_gain_9271
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#define ar9271Modes_high_power_tx_gain_K2 ar9271Modes_high_power_tx_gain_9271
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#include "ar9271.ini"
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/* This is what these are called on the Atheros HAL */
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/* AR9003 2.0 */
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@ -235,7 +309,6 @@ static void ar9001_hw_check_initvals(void)
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}
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#endif /* ATHEROS */
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#ifndef ATHEROS
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static void ar9002_hw_check_initvals(void)
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{
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u64 chksum;
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@ -287,11 +360,6 @@ static void ar9002_hw_check_initvals(void)
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INI_CHECK(ar9271Modes_normal_power_tx_gain_9271, 6);
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INI_CHECK(ar9271Modes_high_power_tx_gain_9271, 6);
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}
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#else
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static void ar9002_hw_check_initvals(void)
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{
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}
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#endif /* ATHEROS */
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static void ar9003_2p0_hw_check_initvals(void)
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{
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@ -403,7 +471,6 @@ static void ar9001_hw_print_initvals(void)
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}
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#endif /* ATHEROS */
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#ifndef ATHEROS
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static void ar9002_hw_print_initvals(void)
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{
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u64 chksum;
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@ -440,8 +507,8 @@ static void ar9002_hw_print_initvals(void)
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INI_PRINT(ar9287PciePhy_clkreq_off_L1_9287_1_0, 2);
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INI_PRINT(ar9287Modes_9287_1_1, 6);
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INI_PRINT(ar9287Common_9287_1_1, 2);
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INI_PRINT(ar9287Common_normal_cck_fir_coeff_92871_1, 2);
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INI_PRINT(ar9287Common_japan_2484_cck_fir_coeff_92871_1, 2);
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INI_PRINT(ar9287Common_normal_cck_fir_coeff_9287_1_1, 2);
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INI_PRINT(ar9287Common_japan_2484_cck_fir_coeff_9287_1_1, 2);
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INI_PRINT(ar9287Modes_tx_gain_9287_1_1, 6);
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INI_PRINT(ar9287Modes_rx_gain_9287_1_1, 6);
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INI_PRINT(ar9287PciePhy_clkreq_always_on_L1_9287_1_1, 2);
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@ -455,11 +522,6 @@ static void ar9002_hw_print_initvals(void)
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INI_PRINT(ar9271Modes_normal_power_tx_gain_9271, 6);
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INI_PRINT(ar9271Modes_high_power_tx_gain_9271, 6);
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}
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#else
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static void ar9002_hw_print_initvals(void)
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{
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}
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#endif /* ATHEROS */
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static void ar9003_2p0_hw_print_initvals(void)
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{
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@ -513,19 +575,16 @@ static void ar9003_2p2_hw_print_initvals(void)
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INI_PRINT(ar9300PciePhy_clkreq_disable_L1_2p2, 2);
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}
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static void usage()
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{
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printf("Usage: initvals [-w] [-f "
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#ifndef ATHEROS
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static void usage()
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{
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printf("Usage: initvals [-w ] [-f ar5008 | ar9001 | ar9002 | ar9003-2p0 | ar9003-2p2 ]\n");
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}
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#else
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static void usage()
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{
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printf("Usage: initvals [-w ] [-f ar9003-2p0 | ar9003-2p2 ]\n");
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}
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"ar5008 | ar9001 | "
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#endif
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"ar9002 | ar9003-2p0 | ar9003-2p2"
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"]\n");
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}
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#ifndef ATHEROS
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print_initvals_family(char *family)
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{
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print_license();
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@ -554,32 +613,7 @@ print_initvals_family(char *family)
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printf("#endif /* INITVALS_9003_2P2_H */\n");
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}
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}
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#else
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print_initvals_family(char *family)
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{
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print_license();
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if (strncmp(family, "ar9003-2p0", 10) == 0) {
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printf("#ifndef INITVALS_9003_H\n");
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printf("#define INITVALS_9003_H\n");
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printf("\n");
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printf("/* AR9003 2.0 */\n");
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printf("\n");
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ar9003_2p0_hw_print_initvals();
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printf("#endif /* INITVALS_9003_H */\n");
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} else if (strncmp(family, "ar9003-2p2", 10) == 0) {
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printf("#ifndef INITVALS_9003_2P2_H\n");
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printf("#define INITVALS_9003_2P2_H\n");
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printf("\n");
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printf("/* AR9003 2.2 */\n");
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printf("\n");
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ar9003_2p2_hw_print_initvals();
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printf("#endif /* INITVALS_9003_2P2_H */\n");
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}
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}
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#endif /* ATHEROS */
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#ifndef ATHEROS
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check_initvals_family(char *family)
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{
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if (strncmp(family, "ar5008", 6) == 0)
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@ -593,15 +627,6 @@ check_initvals_family(char *family)
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else if (strncmp(family, "ar9003-2p2", 10) == 0)
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ar9003_2p2_hw_check_initvals();
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}
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#else
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check_initvals_family(char *family)
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{
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if (strncmp(family, "ar9003-2p0", 10) == 0)
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ar9003_2p0_hw_check_initvals();
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else if (strncmp(family, "ar9003-2p2", 10) == 0)
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ar9003_2p2_hw_check_initvals();
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}
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#endif /* ATHEROS */
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int main(int argc, void *argv[])
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{
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