There is a change in reference clock(XO) frequency of
ipq6018(24MHz) from ipq807x(19.2MHz). Accordingly,
updated the phy init sequence of PCIe.
Change-Id: I86230187a46fec16a87acfaa17cfa27dc1eb728c
Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org>
This device is a non onfi device, so adding the device id and
oob details to nand_ids table.
This device is non onfi device, so adding the device id
and oob information in the nand_ids table.
1.pagesize:2048 bytes
2.oob size:128bytes
3.Ecc:8bits for 512 bytes
4.Man & dev id: 0x98 0xa1
Change-Id: I69763ea28fc3f81a74cacad4338b6d55c42d93b6
Signed-off-by: sameeruddin shaik <samesh@codeaurora.org>
This patch updates the config from c1 to
emulation-c3
c3 config will be used for full boot chain and
c1 config will be used for standalone kernel.
Change-Id: Iffb85184513e5cba38349f638d7eaac7ce020375
Signed-off-by: speriaka <speriaka@codeaurora.org>
The scm parameters are different for ipq6018. Updated
parameters appropriately as needed for supporting both
ipq6018 and ipq807x.
Change-Id: I3413013c29a5afce36361f7a38f930dadfd34a3d
Signed-off-by: speriaka <speriaka@codeaurora.org>
Adding the DSB/ISB instructions in the dcache flush functions
to make sure that the cache flush instruction gets completed
before another instruction executes.
Change-Id: I0bc2222cb040a96cc7413586b9131904bd5d1167
Signed-off-by: sameeruddin shaik <samesh@codeaurora.org>
We have timer enabled by default. We don't want the
register re-written as it is write protected by the
underlying layer.
Change-Id: Ia43e4b973c30a5e492b7d048714b21fc5a56be9e
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
eMMC part THGBMNG5D1LBAIT (Toshiba 4GB) is taking long time for
the secure trim.This leads to erase timeout. Manufacturer ID based
quirk is added for the specific part to use trim instead of secure
trim for block erase.
without this change we can see the error erase timeout and erase failed.
error:
MMC erase: dev # 0, block # 6690, count 2047 ... sdhci_send_command:
MMC: 0 busy timeout increasing to: 2000 ms.
sdhci_send_command: MMC: 0 busy timeout increasing to: 4000 ms.
timeout.
mmc erase failed
-1 blocks erased: ERROR
Change-Id: I1126690400b274bb4735750584d7fb4b105e6618
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
There is a change in reference clock(XO) frequency of
ipq6018(24MHz) from ipq807x(19.2MHz) platform.
So, updated USB phy init sequence. Also, updated
clock init and usb deinit functions.
Change-Id: Ie48867d1c0740562e2c108ef3b2caa187fa95485
Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org>
This patch modifies the SPI devices and SPI
info idx to 2. This is necessary because ipq6018
platform has support for both SPI NOR and
SPI NAND
Change-Id: I0fcdd4a43cd95e4c21b738fda193672fc51bf75f
Signed-off-by: speriaka <speriaka@codeaurora.org>
This is to provide software framework to retain IMEM’s state
across warm reset. For warm reset crashdump collection should be
disabled.
In uboot we will check for the environment variable dload_warm_reset.The
crashdump magic is reset to 0x10 in SDI path, hence disable the SDI bit
in Uboot if environment variable is set which will disable crashdump
collection.
Change-Id: Ic60b63ead03436689ee04d2e3e7ecdbb275ccfee
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
This change will handle masking of DAT inhibit bit of
present state register. This status bit is genarated if
either the DAT Line Active or Read Transfer Active is set to
1. If this bit is 0, it indicates the host controller can issue
the next command.
Commands with busy signal belong to Command Inhibit(DAT).
e.g (R1b, R5b type).
Changing from 1 to 0 generates a transfer complete interrupt
in normal interrupt status register.
If this bit value is 1: Cannot issue command which uses DAT line.
If this bit value is 0: Can issue command which uses DAT line.
This change is masking SDHCI_DATA_INHIBIT bit only if card is in
busy state.
Without this change we can get the erase timeout error.
error:
MMC erase: dev # 0, block # 27682, count 16383 ...
sdhci_send_command: MMC: 0 busy timeout increasing to: 2000 ms.
Change-Id: I0612e576c09a7fd077bed1a1ee717afcddfa7e87
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
In emulation, during full boot chain, usb clocks are
disabled during usb deinit in uboot. In kernel,
we are using dummy clock driver for emulation.
In order for the usb clocks to be enabled while
kernel boot up, skipped usb deinit in uboot.
Change-Id: I47de9da5a6afbed524659e936eb8215e03a99ac0
Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org>
This change will add to support "qce_fixed_key" as
environmen variable. If "qce_fixed_key" environmen variable
set then "qce,use_fixed_hw_key" dts property set in kernel.
This property will use for fixed HW key selection.
Change-Id: I9b94d0a2b4e48dac92eccd95f42bedd8b990b723
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Added support for warm reset to retain IMEM state.
If dload_warm_reset environment variable is set, then dload_status and
dload_warm_reset dts entry in kernel will be set to 1. This will be used for
disabling crashdump and sdi and also to set crashdump magic to 0x20.
Change-Id: Ie8c32e9d619c910d0f12f93374ee45bc1c8379a0
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
