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ipq6018: configuring SDHC1_AHB_CBCR clock

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Change-Id: I818e5cc0da74240a78ffeb15a1765be4501f6756
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
This commit is contained in:
Antony Arun T 2019-03-25 15:29:43 +05:30
parent b0ced6d35e
commit 1d89a6f1da
2 changed files with 2 additions and 0 deletions
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1
board/qca/arm/ipq6018/ipq6018.c
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@ -146,6 +146,7 @@ void emmc_clock_config()
writel(readl(GCC_SDCC1_APPS_CBCR)|0x1, GCC_SDCC1_APPS_CBCR);
/* Add 10us delay for CLK_OFF to get cleared */
udelay(10);
writel(readl(GCC_SDCC1_AHB_CBCR)|0x1, GCC_SDCC1_AHB_CBCR);
/* PLL0 - 192Mhz */
writel(0x20B, GCC_SDCC1_APPS_CFG_RCGR);
/* Delay for clock operation complete */

1
board/qca/arm/ipq6018/ipq6018.h
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@ -30,6 +30,7 @@
#define GCC_SDCC1_APPS_D 0x1842014
#define GCC_BLSP1_UART1_APPS_CBCR 0x0180203c
#define GCC_SDCC1_BCR 0x01842000
#define GCC_SDCC1_AHB_CBCR 0x0184201C
#define GCC_BLSP1_UART2_APPS_CFG_RCGR 0x01803038
#define GCC_BLSP1_UART2_APPS_M 0x0180303C