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ipq6018: Enabling Ethernet support

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Change-Id: If49c5b86fb08bda0ab29d7663fa0f8fca9a9f5bb
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
This commit is contained in:
Antony Arun T 2019-01-29 10:22:32 +05:30
parent 0164b14f3e
commit f5e48f3e59
10 changed files with 4770 additions and 0 deletions
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398
arch/arm/include/asm/arch-ipq6018/edma_regs.h Normal file
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@ -0,0 +1,398 @@
/*
**************************************************************************
* Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
**************************************************************************
*/
#ifndef __EDMA_REGS__
#define __EDMA_REGS__
#define IPQ6018_EDMA_CFG_BASE 0x3ab00000
/*
* IPQ6018 EDMA register offsets
*/
#define IPQ6018_EDMA_REG_MAS_CTRL 0x0
#define IPQ6018_EDMA_REG_PORT_CTRL 0x4
#define IPQ6018_EDMA_REG_VLAN_CTRL 0x8
#define IPQ6018_EDMA_REG_TXDESC2CMPL_MAP_0 0xc
#define IPQ6018_EDMA_REG_TXDESC2CMPL_MAP_1 0x10
#define IPQ6018_EDMA_REG_TXDESC2CMPL_MAP_2 0x14
#define IPQ6018_EDMA_REG_RXDESC2FILL_MAP_0 0x18
#define IPQ6018_EDMA_REG_RXDESC2FILL_MAP_1 0x1c
#define IPQ6018_EDMA_REG_TXQ_CTRL 0x20
#define IPQ6018_EDMA_REG_TXQ_CTRL_2 0x24
#define IPQ6018_EDMA_REG_TXQ_FC_0 0x28
#define IPQ6018_EDMA_REG_TXQ_FC_1 0x30
#define IPQ6018_EDMA_REG_TXQ_FC_2 0x34
#define IPQ6018_EDMA_REG_TXQ_FC_3 0x38
#define IPQ6018_EDMA_REG_RXQ_CTRL 0x3c
#define IPQ6018_EDMA_REG_RX_TX_FULL_QID 0x40
#define IPQ6018_EDMA_REG_RXQ_FC_THRE 0x44
#define IPQ6018_EDMA_REG_DMAR_CTRL 0x48
#define IPQ6018_EDMA_REG_AXIR_CTRL 0x4c
#define IPQ6018_EDMA_REG_AXIW_CTRL 0x50
#define IPQ6018_EDMA_REG_MIN_MSS 0x54
#define IPQ6018_EDMA_REG_LOOPBACK_CTRL 0x58
#define IPQ6018_EDMA_REG_MISC_INT_STAT 0x5c
#define IPQ6018_EDMA_REG_MISC_INT_MASK 0x60
#define IPQ6018_EDMA_REG_DBG_CTRL 0x64
#define IPQ6018_EDMA_REG_DBG_DATA 0x68
#define IPQ6018_EDMA_REG_TXDESC_BA(n) (0x1000 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXDESC_PROD_IDX(n) (0x1004 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXDESC_CONS_IDX(n) (0x1008 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXDESC_RING_SIZE(n) (0x100c + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXDESC_CTRL(n) (0x1010 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_BA(n) (0x19000 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_PROD_IDX(n) (0x19004 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_CONS_IDX(n) (0x19008 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_RING_SIZE(n) (0x1900c + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_UGT_THRE(n) (0x19010 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_CTRL(n) (0x19014 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TXCMPL_BPC(n) (0x19018 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TX_INT_STAT(n) (0x21000 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TX_INT_MASK(n) (0x21004 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TX_MOD_TIMER(n) (0x21008 + (0x1000 * n))
#define IPQ6018_EDMA_REG_TX_INT_CTRL(n) (0x2100c + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXFILL_BA(n) (0x29000 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXFILL_PROD_IDX(n) (0x29004 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXFILL_CONS_IDX(n) (0x29008 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXFILL_RING_SIZE(n) (0x2900c + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXFILL_BUFFER1_SIZE(n) (0x29010 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXFILL_FC_THRE(n) (0x29014 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXFILL_UGT_THRE(n) (0x29018 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXFILL_RING_EN(n) (0x2901c + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXFILL_DISABLE(n) (0x29020 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXFILL_DISABLE_DONE(n) (0x29024 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXFILL_INT_STAT(n) (0x31000 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXFILL_INT_MASK(n) (0x31004 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXDESC_BA(n) (0x39000 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXDESC_PROD_IDX(n) (0x39004 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXDESC_CONS_IDX(n) (0x39008 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXDESC_RING_SIZE(n) (0x3900c + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXDESC_FC_THRE(n) (0x39010 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXDESC_UGT_THRE(n) (0x39014 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXDESC_CTRL(n) (0x39018 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXDESC_BPC(n) (0x3901c + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXDESC_INT_STAT(n) (0x49000 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RXDESC_INT_MASK(n) (0x49004 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RX_MOD_TIMER(n) (0x49008 + (0x1000 * n))
#define IPQ6018_EDMA_REG_RX_INT_CTRL(n) (0x4900c + (0x1000 * n))
#define IPQ6018_EDMA_QID2RID_TABLE_MEM(q) (0x5a000 + (0x4 * q))
#define IPQ6018_EDMA_REG_RXRING_PC(n) (0x5A200 + (0x10 * n))
#define IPQ6018_EDMA_REG_RXRING_BC_0(n) (0x5A204 + (0x10 * n))
#define IPQ6018_EDMA_REG_RXRING_BC_1(n) (0x5A208 + (0x10 * n))
#define IPQ6018_EDMA_REG_TXRING_PC(n) (0x74000 + (0x10 * n))
#define IPQ6018_EDMA_REG_TXRING_BC_0(n) (0x74004 + (0x10 * n))
#define IPQ6018_EDMA_REG_TXRING_BC_1(n) (0x74008 + (0x10 * n))
/*
* EDMA_REG_PORT_CTRL register
*/
#define IPQ6018_EDMA_PORT_CTRL_EN 0x3
#define IPQ6018_EDMA_PORT_CTRL_PAD_EN 0x1
/*
* EDMA_REG_TXQ_CTRL register
*/
#define IPQ6018_EDMA_TXDESC_PF_THRE_MASK 0xf
#define IPQ6018_EDMA_TXDESC_PF_THRE_SHIFT 0
#define IPQ6018_EDMA_TXCMPL_WB_THRE_MASK 0xf
#define IPQ6018_EDMA_TXCMPL_WB_THRE_SHIFT 4
#define IPQ6018_EDMA_TXDESC_PKT_SRAM_THRE_MASK 0xff
#define IPQ6018_EDMA_TXDESC_PKT_SRAM_THRE_SHIFT 8
#define IPQ6018_EDMA_TXCMPL_WB_TIMER_MASK 0xffff
#define IPQ6018_EDMA_TXCMPL_WB_TIMER_SHIFT 16
/*
* EDMA_REG_RXQ_CTRL register
*/
#define IPQ6018_EDMA_RXFILL_PF_THRE_MASK 0xf
#define IPQ6018_EDMA_RXFILL_PF_THRE_SHIFT 0
#define IPQ6018_EDMA_RXDESC_WB_THRE_MASK 0xf
#define IPQ6018_EDMA_RXDESC_WB_THRE_SHIFT 4
#define IPQ6018_EDMA_RXDESC_WB_TIMER_MASK 0xffff
#define IPQ6018_EDMA_RXDESC_WB_TIMER_SHIFT 16
/*
* EDMA_REG_RX_TX_FULL_QID register
*/
#define IPQ6018_EDMA_RX_DESC_FULL_QID_MASK 0xff
#define IPQ6018_EDMA_RX_DESC_FULL_QID_SHIFT 0
#define IPQ6018_EDMA_TX_CMPL_BUF_FULL_QID_MASK 0xff
#define IPQ6018_EDMA_TX_CMPL_BUF_FULL_QID_SHIFT 8
#define IPQ6018_EDMA_TX_SRAM_FULL_QID_MASK 0x1f
#define IPQ6018_EDMA_TX_SRAM_FULL_QID_SHIFT 16
/*
* EDMA_REG_RXQ_FC_THRE reister
*/
#define IPQ6018_EDMA_RXFILL_FIFO_XOFF_THRE_MASK 0x1f
#define IPQ6018_EDMA_RXFILL_FIFO_XOFF_THRE_SHIFT 0
#define IPQ6018_EDMA_DESC_FIFO_XOFF_THRE_MASK 0x3f
#define IPQ6018_EDMA_DESC_FIFO_XOFF_THRE_SHIFT 16
/*
* EDMA_REG_DMAR_CTRL register
*/
#define IPQ6018_EDMA_DMAR_REQ_PRI_MASK 0x7
#define IPQ6018_EDMA_DMAR_REQ_PRI_SHIFT 0
#define IPQ6018_EDMA_DMAR_BURST_LEN_MASK 0x1
#define IPQ6018_EDMA_DMAR_BURST_LEN_SHIFT 3
#define IPQ6018_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_MASK 0x1f
#define IPQ6018_EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SHIFT 4
#define IPQ6018_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_MASK 0x7
#define IPQ6018_EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SHIFT 9
#define IPQ6018_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_MASK 0x7
#define IPQ6018_EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SHIFT 12
/*
* EDMA DISABLE
*/
#define IPQ6018_EDMA_DISABLE 0
/*
* EDMA_REG_TXDESC_PROD_IDX register
*/
#define IPQ6018_EDMA_TXDESC_PROD_IDX_MASK 0xffff
/*
* EDMA_REG_TXDESC_CONS_IDX register
*/
#define IPQ6018_EDMA_TXDESC_CONS_IDX_MASK 0xffff
/*
* EDMA_REG_TXDESC_RING_SIZE register
*/
#define IPQ6018_EDMA_TXDESC_RING_SIZE_MASK 0xffff
/*
* EDMA_REG_TXDESC_CTRL register
*/
#define IPQ6018_EDMA_TXDESC_ARB_GRP_ID_MASK 0x3
#define IPQ6018_EDMA_TXDESC_ARB_GRP_ID_SHIFT 4
#define IPQ6018_EDMA_TXDESC_FC_GRP_ID_MASK 0x7
#define IPQ6018_EDMA_TXDESC_FC_GRP_ID_SHIFT 1
#define IPQ6018_EDMA_TXDESC_TX_EN 0x1
/*
* EDMA_REG_TXCMPL_PROD_IDX register
*/
#define IPQ6018_EDMA_TXCMPL_PROD_IDX_MASK 0xffff
/*
* EDMA_REG_TXCMPL_CONS_IDX register
*/
#define IPQ6018_EDMA_TXCMPL_CONS_IDX_MASK 0xffff
/*
* EDMA_REG_TXCMPL_RING_SIZE register
*/
#define IPQ6018_EDMA_TXCMPL_RING_SIZE_MASK 0xffff
/*
* EDMA_REG_TXCMPL_UGT_THRE register
*/
#define IPQ6018_EDMA_TXCMPL_LOW_THRE_MASK 0xffff
#define IPQ6018_EDMA_TXCMPL_LOW_THRE_SHIFT 0
#define IPQ6018_EDMA_TXCMPL_FC_THRE_MASK 0x3f
#define IPQ6018_EDMA_TXCMPL_FC_THRE_SHIFT 16
/*
* EDMA_REG_TXCMPL_CTRL register
*/
#define IPQ6018_EDMA_TXCMPL_RET_MODE_BUFF_ADDR 0x0
#define IPQ6018_EDMA_TXCMPL_RET_MODE_OPAQUE 0x1
/*
* EDMA_REG_TX_MOD_TIMER register
*/
#define IPQ6018_EDMA_TX_MOD_TIMER_INIT_MASK 0xffff
#define IPQ6018_EDMA_TX_MOD_TIMER_INIT_SHIFT 0
/*
* EDMA_REG_TX_INT_CTRL register
*/
#define IPQ6018_EDMA_TX_INT_MASK 0x3
/*
* EDMA_REG_RXFILL_PROD_IDX register
*/
#define IPQ6018_EDMA_RXFILL_PROD_IDX_MASK 0xffff
/*
* EDMA_REG_RXFILL_CONS_IDX register
*/
#define IPQ6018_EDMA_RXFILL_CONS_IDX_MASK 0xffff
/*
* EDMA_REG_RXFILL_RING_SIZE register
*/
#define IPQ6018_EDMA_RXFILL_RING_SIZE_MASK 0xffff
#define IPQ6018_EDMA_RXFILL_BUF_SIZE_MASK 0x3fff
#define IPQ6018_EDMA_RXFILL_BUF_SIZE_SHIFT 16
/*
* EDMA_REG_RXFILL_FC_THRE register
*/
#define IPQ6018_EDMA_RXFILL_FC_XON_THRE_MASK 0x7ff
#define IPQ6018_EDMA_RXFILL_FC_XON_THRE_SHIFT 12
#define IPQ6018_EDMA_RXFILL_FC_XOFF_THRE_MASK 0x7ff
#define IPQ6018_EDMA_RXFILL_FC_XOFF_THRE_SHIFT 0
/*
* EDMA_REG_RXFILL_UGT_THRE register
*/
#define IPQ6018_EDMA_RXFILL_LOW_THRE_MASK 0xffff
#define IPQ6018_EDMA_RXFILL_LOW_THRE_SHIFT 0
/*
* EDMA_REG_RXFILL_RING_EN register
*/
#define IPQ6018_EDMA_RXFILL_RING_EN 0x1
/*
* EDMA_REG_RXFILL_INT_MASK register
*/
#define IPQ6018_EDMA_RXFILL_INT_MASK 0x1
/*
* EDMA_REG_RXDESC_PROD_IDX register
*/
#define IPQ6018_EDMA_RXDESC_PROD_IDX_MASK 0xffff
/*
* EDMA_REG_RXDESC_CONS_IDX register
*/
#define IPQ6018_EDMA_RXDESC_CONS_IDX_MASK 0xffff
/*
* EDMA_REG_RXDESC_RING_SIZE register
*/
#define IPQ6018_EDMA_RXDESC_RING_SIZE_MASK 0xffff
#define IPQ6018_EDMA_RXDESC_PL_OFFSET_MASK 0x1ff
#define IPQ6018_EDMA_RXDESC_PL_OFFSET_SHIFT 16
/*
* EDMA_REG_RXDESC_FC_THRE register
*/
#define IPQ6018_EDMA_RXDESC_FC_XON_THRE_MASK 0x7ff
#define IPQ6018_EDMA_RXDESC_FC_XON_THRE_SHIFT 12
#define IPQ6018_EDMA_RXDESC_FC_XOFF_THRE_MASK 0x7ff
#define IPQ6018_EDMA_RXDESC_FC_XOFF_THRE_SHIFT 0
/*
* EDMA_REG_RXDESC_UGT_THRE register
*/
#define IPQ6018_EDMA_RXDESC_LOW_THRE_MASK 0xffff
#define IPQ6018_EDMA_RXDESC_LOW_THRE_SHIFT 0
/*
* EDMA_REG_RXDESC_CTRL register
*/
#define IPQ6018_EDMA_RXDESC_STAG_REMOVE_EN 0x8
#define IPQ6018_EDMA_RXDESC_CTAG_REMOVE_EN 0x4
#define IPQ6018_EDMA_RXDESC_QDISC_EN 0x2
#define IPQ6018_EDMA_RXDESC_RX_EN 0x1
/*
* EDMA_REG_TX_INT_MASK register
*/
#define IPQ6018_EDMA_TX_INT_MASK_PKT_INT 0x1
#define IPQ6018_EDMA_TX_INT_MASK_UGT_INT 0x2
/*
* EDMA_REG_RXDESC_INT_STAT register
*/
#define IPQ6018_EDMA_RXDESC_INT_STAT_PKT_INT 0x1
#define IPQ6018_EDMA_RXDESC_INT_STAT_UGT_INT 0x2
/*
* EDMA_REG_RXDESC_INT_MASK register
*/
#define IPQ6018_EDMA_RXDESC_INT_MASK_PKT_INT 0x1
#define IPQ6018_EDMA_RXDESC_INT_MASK_TIMER_INT_DIS 0x2
#define IPQ6018_EDMA_MASK_INT_DISABLE 0x0
#define IPQ6018_EDMA_MASK_INT_CLEAR 0x0
/*
* EDMA_REG_RX_MOD_TIMER register
*/
#define IPQ6018_EDMA_RX_MOD_TIMER_INIT_MASK 0xffff
#define IPQ6018_EDMA_RX_MOD_TIMER_INIT_SHIFT 0
/*
* EDMA QID2RID register sizes
*/
#define IPQ6018_EDMA_QID2RID_DEPTH 0x40
#define IPQ6018_EDMA_QID2RID_QUEUES_PER_ENTRY 8
/*
* TXDESC shift values
*/
#define IPQ6018_EDMA_TXDESC_MORE_SHIFT 31
#define IPQ6018_EDMA_TXDESC_TSO_EN_SHIFT 30
#define IPQ6018_EDMA_TXDESC_PREHEADER_SHIFT 29
#define IPQ6018_EDMA_TXDESC_POOL_ID_SHIFT 24
#define IPQ6018_EDMA_TXDESC_POOL_ID_MASK 0x1f
#define IPQ6018_EDMA_TXDESC_DATA_OFFSET_SHIFT 16
#define IPQ6018_EDMA_TXDESC_DATA_OFFSET_MASK 0xff
#define IPQ6018_EDMA_TXDESC_DATA_LENGTH_SHIFT 0
#define IPQ6018_EDMA_TXDESC_DATA_LENGTH_MASK 0xffff
#define IPQ6018_EDMA_PREHDR_DSTINFO_PORTID_IND 0x20
#define IPQ6018_EDMA_PREHDR_PORTNUM_BITS 0x0fff
#define IPQ6018_EDMA_RING_DMA_MASK 0xffffffff
/*
* RXDESC shift values
*/
#define IPQ6018_EDMA_RXDESC_RX_RXFILL_CNT_MASK 0x000f
#define IPQ6018_EDMA_RXDESC_RX_RXFILL_CNT_SHIFT 16
#define IPQ6018_EDMA_RXDESC_PKT_SIZE_MASK 0x3fff
#define IPQ6018_EDMA_RXDESC_PKT_SIZE_SHIFT 0
#define IPQ6018_EDMA_RXDESC_RXD_VALID_MASK 0x1
#define IPQ6018_EDMA_RXDESC_RXD_VALID_SHIFT 31
#define IPQ6018_EDMA_RXDESC_PACKET_LEN_MASK 0x3fff
#define IPQ6018_EDMA_RXDESC_RING_INT_STATUS_MASK 0x3
#define IPQ6018_EDMA_RING_DISABLE 0
#define IPQ6018_EDMA_TXCMPL_RING_INT_STATUS_MASK 0x3
#define IPQ6018_EDMA_TXCMPL_RETMODE_OPAQUE 0x0
#define IPQ6018_EDMA_RXFILL_RING_INT_STATUS_MASK 0x1
/*
* TODO tune the timer and threshold values
*/
#define IPQ6018_EDMA_RXFILL_FIFO_XOFF_THRE 0x3
#define IPQ6018_EDMA_RXFILL_PF_THRE 0x3
#define IPQ6018_EDMA_RXDESC_WB_THRE 0x0
#define IPQ6018_EDMA_RXDESC_WB_TIMER 0x2
#define IPQ6018_EDMA_RXDESC_XON_THRE 50
#define IPQ6018_EDMA_RXDESC_XOFF_THRE 30
#define IPQ6018_EDMA_RXDESC_LOW_THRE 0
#define IPQ6018_EDMA_RX_MOD_TIMER_INIT 1000
#define IPQ6018_EDMA_TXDESC_PF_THRE 0x3
#define IPQ6018_EDMA_TXCMPL_WB_THRE 0X0
#define IPQ6018_EDMA_TXDESC_PKT_SRAM_THRE 0x20
#define IPQ6018_EDMA_TXCMPL_WB_TIMER 0x2
#define IPQ6018_EDMA_TX_MOD_TIMER 150
#endif /* __EDMA_REGS__ */

130
board/qca/arm/ipq6018/ipq6018.c
View file

@ -28,6 +28,7 @@
DECLARE_GLOBAL_DATA_PTR;
struct sdhci_host mmc_host;
extern int ipq6018_edma_init(void *cfg);
const char *rsvd_node = "/reserved-memory";
const char *del_node[] = {"uboot",
@ -729,6 +730,135 @@ int set_uuid_bootargs(char *boot_args, char *part_name, int buflen, bool gpt_fla
return 0;
}
int get_napa_gpio(int napa_gpio[2])
{
int napa_gpio_cnt = -1, node;
int res = -1;
node = fdt_path_offset(gd->fdt_blob, "/ess-switch");
if (node >= 0) {
napa_gpio_cnt = fdtdec_get_uint(gd->fdt_blob, node, "napa_gpio_cnt", -1);
if (napa_gpio_cnt >= 1) {
res = fdtdec_get_int_array(gd->fdt_blob, node, "napa_gpio",
(u32 *)napa_gpio, napa_gpio_cnt);
if (res >= 0)
return napa_gpio_cnt;
}
}
return res;
}
void napa_phy_reset_init(void)
{
int napa_gpio[2] = {0}, napa_gpio_cnt, i;
unsigned int *napa_gpio_base;
napa_gpio_cnt = get_napa_gpio(napa_gpio);
if (napa_gpio_cnt >= 1) {
for (i = 0; i < napa_gpio_cnt; i++) {
if (napa_gpio[i] >=0) {
napa_gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(napa_gpio[i]);
writel(0x203, napa_gpio_base);
gpio_direction_output(napa_gpio[i], 0x0);
}
}
}
}
void napa_phy_reset_init_done(void)
{
int napa_gpio[2] = {0}, napa_gpio_cnt, i;
napa_gpio_cnt = get_napa_gpio(napa_gpio);
if (napa_gpio_cnt >= 1) {
for (i = 0; i < napa_gpio_cnt; i++)
gpio_set_value(napa_gpio[i], 0x1);
}
}
void eth_clock_enable(void)
{
int tlmm_base = 0x1025000;
/*
* ethernet clk rcgr block init -- start
* these clk init will be moved to sbl later
*/
writel(0x100 ,0x01868024);
writel(0x1 ,0x01868020);
writel(0x2 ,0x01868020);
writel(0x100 ,0x0186802C);
writel(0x1 ,0x01868028);
writel(0x2 ,0x01868028);
writel(0x100 ,0x01868034);
writel(0x1 ,0x01868030);
writel(0x2 ,0x01868030);
writel(0x100 ,0x0186803C);
writel(0x1 ,0x01868038);
writel(0x2 ,0x01868038);
writel(0x100 ,0x01868044);
writel(0x1 ,0x01868040);
writel(0x2 ,0x01868040);
writel(0x100 ,0x0186804C);
writel(0x1 ,0x01868048);
writel(0x2 ,0x01868048);
writel(0x100 ,0x01868054);
writel(0x1 ,0x01868050);
writel(0x2 ,0x01868050);
writel(0x100 ,0x0186805C);
writel(0x1 ,0x01868058);
writel(0x2 ,0x01868058);
writel(0x100 ,0x01868064);
writel(0x1 ,0x01868060);
writel(0x2 ,0x01868060);
writel(0x100 ,0x0186806C);
writel(0x1 ,0x01868068);
writel(0x2 ,0x01868068);
writel(0x100 ,0x01868074);
writel(0x1 ,0x01868070);
writel(0x2 ,0x01868070);
writel(0x100 ,0x0186807C);
writel(0x1 ,0x01868078);
writel(0x2 ,0x01868078);
writel(0x101 ,0x01868084);
writel(0x1 ,0x01868080);
writel(0x2 ,0x01868080);
writel(0x100 ,0x0186808C);
writel(0x1 ,0x01868088);
writel(0x2 ,0x01868088);
/*
* ethernet clk rcgr block init -- end
* these clk init will be moved to sbl later
*/
/* bring phy out of reset */
writel(7, tlmm_base + 0x1f000);
writel(7, tlmm_base + 0x20000);
writel(0x203, tlmm_base);
writel(0, tlmm_base + 0x4);
napa_phy_reset_init();
mdelay(500);
writel(2, tlmm_base + 0x4);
napa_phy_reset_init_done();
mdelay(500);
}
int board_eth_init(bd_t *bis)
{
int ret=0;
eth_clock_enable();
ret = ipq6018_edma_init(NULL);
if (ret != 0)
printf("%s: ipq6018_edma_init failed : %d\n", __func__, ret);
return ret;
}
unsigned long timer_read_counter(void)
{
return 0;

3
drivers/net/Makefile
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@ -83,6 +83,9 @@ obj-$(CONFIG_IPQ_SWITCH_QCA8511) += ipq806x/qca8511.o
obj-$(CONFIG_IPQ807X_EDMA) += ipq807x/ipq807x_edma.o
obj-$(CONFIG_IPQ807X_EDMA) += ipq807x/ipq807x_ppe.o
obj-$(CONFIG_IPQ807X_EDMA) += ipq807x/ipq807x_uniphy.o
obj-$(CONFIG_IPQ6018_EDMA) += ipq6018/ipq6018_edma.o
obj-$(CONFIG_IPQ6018_EDMA) += ipq6018/ipq6018_ppe.o
obj-$(CONFIG_IPQ6018_EDMA) += ipq6018/ipq6018_uniphy.o
obj-$(CONFIG_IPQ_MDIO) += ipq_common/ipq_mdio.o
obj-$(CONFIG_QCA8075_PHY) += ipq_common/ipq_qca8075.o
obj-$(CONFIG_QCA8033_PHY) += ipq_common/ipq_qca8033.o

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drivers/net/ipq6018/ipq6018_edma.c Executable file
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327
drivers/net/ipq6018/ipq6018_edma.h Normal file
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@ -0,0 +1,327 @@
/*
**************************************************************************
* Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
**************************************************************************
*/
#ifndef __IPQ6018_EDMA__
#define __IPQ6018_EDMA__
#define IPQ6018_NSS_DP_START_PHY_PORT 1
#define IPQ6018_NSS_DP_MAX_PHY_PORTS 6
#define IPQ6018_EDMA_BUF_SIZE 2000
#define IPQ6018_EDMA_DEVICE_NODE_NAME "edma"
#define IPQ6018_EDMA_RX_BUFF_SIZE (IPQ6018_EDMA_BUF_SIZE + IPQ6018_EDMA_RX_PREHDR_SIZE)
#define IPQ6018_EDMA_RX_PREHDR_SIZE (sizeof(struct ipq6018_edma_rx_preheader))
#define IPQ6018_EDMA_TX_PREHDR_SIZE (sizeof(struct ipq6018_edma_tx_preheader))
#define IPQ6018_EDMA_TXDESC_RING_SIZE 8
#define IPQ6018_EDMA_TXCMPL_RING_SIZE 8
#define IPQ6018_EDMA_RXDESC_RING_SIZE 16
#define IPQ6018_EDMA_RXFILL_RING_SIZE 16
#define IPQ6018_EDMA_START_GMACS IPQ6018_NSS_DP_START_PHY_PORT
#define IPQ6018_EDMA_MAX_GMACS IPQ6018_NSS_DP_MAX_PHY_PORTS
#define IPQ6018_EDMA_TX_BUF_SIZE (1540 + IPQ6018_EDMA_TX_PREHDR_SIZE)
#define IPQ6018_EDMA_MAX_TXCMPL_RINGS 8 /* Max TxCmpl rings */
#define IPQ6018_EDMA_MAX_RXDESC_RINGS 16 /* Max RxDesc rings */
#define IPQ6018_EDMA_MAX_RXFILL_RINGS 8 /* Max RxFill rings */
#define IPQ6018_EDMA_MAX_TXDESC_RINGS 24 /* Max TxDesc rings */
#define IPQ6018_EDMA_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
#define IPQ6018_EDMA_RXFILL_DESC(R, i) IPQ6018_EDMA_GET_DESC(R, i, struct ipq6018_edma_rxfill_desc)
#define IPQ6018_EDMA_RXDESC_DESC(R, i) IPQ6018_EDMA_GET_DESC(R, i, struct ipq6018_edma_rxdesc_desc)
#define IPQ6018_EDMA_TXDESC_DESC(R, i) IPQ6018_EDMA_GET_DESC(R, i, struct ipq6018_edma_txdesc_desc)
#define IPQ6018_EDMA_TXCMPL_DESC(R, i) IPQ6018_EDMA_GET_DESC(R, i, struct ipq6018_edma_txcmpl_desc)
#define IPQ6018_EDMA_RXPH_SRC_INFO_TYPE_GET(rxph) (((rxph)->src_info >> 8) & 0xf0)
#define IPQ6018_EDMA_DEV 1
#define IPQ6018_EDMA_TX_QUEUE 1
#define IPQ6018_EDMA_RX_QUEUE 1
//#define IPQ6018_EDMA_TX_DESC_RING_START 23
#define IPQ6018_EDMA_TX_DESC_RING_START 0
#define IPQ6018_EDMA_TX_DESC_RING_NOS 1
#define IPQ6018_EDMA_TX_DESC_RING_SIZE \
(IPQ6018_EDMA_TX_DESC_RING_START + IPQ6018_EDMA_TX_DESC_RING_NOS)
#define IPQ6018_EDMA_TX_CMPL_RING_START 7
#define IPQ6018_EDMA_TX_CMPL_RING_NOS 1
#define IPQ6018_EDMA_TX_CMPL_RING_SIZE \
(IPQ6018_EDMA_TX_CMPL_RING_START + IPQ6018_EDMA_TX_CMPL_RING_NOS)
#define IPQ6018_EDMA_RX_DESC_RING_START 15
#define IPQ6018_EDMA_RX_DESC_RING_NOS 1
#define IPQ6018_EDMA_RX_DESC_RING_SIZE \
(IPQ6018_EDMA_RX_DESC_RING_START + IPQ6018_EDMA_RX_DESC_RING_NOS)
#define IPQ6018_EDMA_RX_FILL_RING_START 7
#define IPQ6018_EDMA_RX_FILL_RING_NOS 1
#define IPQ6018_EDMA_RX_FILL_RING_SIZE \
(IPQ6018_EDMA_RX_FILL_RING_START + IPQ6018_EDMA_RX_FILL_RING_NOS)
#define IPQ6018_EDMA_TX_IMR_NORMAL_MASK 1
#define IPQ6018_EDMA_RX_IMR_NORMAL_MASK 1
#define IPQ6018_EDMA_INTR_CLEAR_TYPE 0
#define IPQ6018_EDMA_INTR_SW_IDX_W_TYPE 0
#define IPQ6018_EDMA_RSS_TYPE_NONE 0x1
#define NETDEV_TX_BUSY 1
#define PSGMIIPHY_PLL_VCO_RELATED_CTRL 0x0009878c
#define PSGMIIPHY_PLL_VCO_VAL 0x2803
#define PSGMIIPHY_VCO_CALIBRATION_CTRL 0x0009809c
#define PSGMIIPHY_VCO_VAL 0x4ADA
#define PSGMIIPHY_VCO_RST_VAL 0xADA
#define RGMII_TCSR_ESS_CFG 0x01953000
#define ESS_RGMII_CTRL 0x0C000004
/*
* Tx descriptor
*/
struct ipq6018_edma_txdesc_desc {
uint32_t buffer_addr;
/* buffer address */
uint32_t word1;
/* more bit, TSO, preheader, pool, offset and length */
};
/*
* TxCmpl descriptor
*/
struct ipq6018_edma_txcmpl_desc {
uint32_t buffer_addr; /* buffer address/opaque */
uint32_t status; /* status */
};
/*
* Rx descriptor
*/
struct ipq6018_edma_rxdesc_desc {
uint32_t buffer_addr; /* buffer address */
uint32_t status; /* status */
};
/*
* RxFill descriptor
*/
struct ipq6018_edma_rxfill_desc {
uint32_t buffer_addr; /* Buffer address */
uint32_t word1; /* opaque_ind and buffer size */
};
/*
* Tx descriptor ring
*/
struct ipq6018_edma_txdesc_ring {
uint32_t id; /* TXDESC ring number */
void *desc; /* descriptor ring virtual address */
dma_addr_t dma; /* descriptor ring physical address */
uint16_t count; /* number of descriptors */
};
/*
* TxCmpl ring
*/
struct ipq6018_edma_txcmpl_ring {
uint32_t id; /* TXCMPL ring number */
void *desc; /* descriptor ring virtual address */
dma_addr_t dma; /* descriptor ring physical address */
uint16_t count; /* number of descriptors in the ring */
};
/*
* RxFill ring
*/
struct ipq6018_edma_rxfill_ring {
uint32_t id; /* RXFILL ring number */
void *desc; /* descriptor ring virtual address */
dma_addr_t dma; /* descriptor ring physical address */
uint16_t count; /* number of descriptors in the ring */
};
/*
* RxDesc ring
*/
struct ipq6018_edma_rxdesc_ring {
uint32_t id; /* RXDESC ring number */
struct ipq6018_edma_rxfill_ring *rxfill; /* RXFILL ring used */
void *desc; /* descriptor ring virtual address */
dma_addr_t dma; /* descriptor ring physical address */
uint16_t count; /* number of descriptors in the ring */
};
/*
* EDMA Tx Preheader
*/
struct ipq6018_edma_tx_preheader {
uint32_t opaque; /* Opaque, contains skb pointer */
uint16_t src_info; /* Src information */
uint16_t dst_info; /* Dest information */
uint32_t tx_pre2; /* SVLAN & CVLAN flag, drop prec, hash value */
uint32_t tx_pre3; /* STAG, CTAG */
uint32_t tx_pre4; /* CPU code, L3 & L4 offset, service code */
uint32_t tx_pre5; /* IP addr index, ACL index */
uint32_t tx_pre6; /* IP payload checksum, copy2cpu, timestamp, dscp */
uint32_t tx_pre7; /* Timestamp, QoS TAG */
};
/*
* EDMA Rx Preheader
*/
struct ipq6018_edma_rx_preheader {
uint32_t opaque; /* Opaque, contains skb pointer*/
uint16_t src_info; /* Src information */
uint16_t dst_info; /* Dest information */
uint32_t rx_pre2; /* SVLAN & CVLAN flag, drop prec, hash value */
uint32_t rx_pre3; /* STAG, CTAG */
uint32_t rx_pre4; /* CPU code, L3 & L4 offset, service code */
uint32_t rx_pre5; /* IP addr index, ACL index */
uint32_t rx_pre6; /* IP payload checksum, copy2cpu, timestamp, dscp */
uint32_t rx_pre7; /* Timestamp, QoS TAG */
};
enum ipq6018_edma_tx {
EDMA_TX_OK = 0, /* Tx success */
EDMA_TX_DESC = 1, /* Not enough descriptors */
EDMA_TX_FAIL = 2, /* Tx failure */
};
/* per core queue related information */
struct queue_per_cpu_info {
u32 tx_mask; /* tx interrupt mask */
u32 rx_mask; /* rx interrupt mask */
u32 tx_status; /* tx interrupt status */
u32 rx_status; /* rx interrupt status */
u32 tx_start; /* tx queue start */
u32 rx_start; /* rx queue start */
struct ipq6018_edma_common_info *c_info; /* edma common info */
};
/* edma hw specific data */
struct ipq6018_edma_hw {
unsigned long __iomem *hw_addr; /* inner register address */
u8 intr_clear_type; /* interrupt clear */
u8 intr_sw_idx_w; /* To do chk type interrupt software index */
u16 rx_buff_size; /* To do chk type Rx buffer size */
u8 rss_type; /* rss protocol type */
uint16_t rx_payload_offset; /* start of the payload offset */
uint32_t flags; /* internal flags */
int active; /* status */
struct ipq6018_edma_txdesc_ring *txdesc_ring; /* Tx Descriptor Ring, SW is producer */
struct ipq6018_edma_txcmpl_ring *txcmpl_ring; /* Tx Completion Ring, SW is consumer */
struct ipq6018_edma_rxdesc_ring *rxdesc_ring; /* Rx Descriptor Ring, SW is consumer */
struct ipq6018_edma_rxfill_ring *rxfill_ring; /* Rx Fill Ring, SW is producer */
uint32_t txdesc_rings; /* Number of TxDesc rings */
uint32_t txdesc_ring_start; /* Id of first TXDESC ring */
uint32_t txdesc_ring_end; /* Id of the last TXDESC ring */
uint32_t txcmpl_rings; /* Number of TxCmpl rings */
uint32_t txcmpl_ring_start; /* Id of first TXCMPL ring */
uint32_t txcmpl_ring_end; /* Id of last TXCMPL ring */
uint32_t rxfill_rings; /* Number of RxFill rings */
uint32_t rxfill_ring_start; /* Id of first RxFill ring */
uint32_t rxfill_ring_end; /* Id of last RxFill ring */
uint32_t rxdesc_rings; /* Number of RxDesc rings */
uint32_t rxdesc_ring_start; /* Id of first RxDesc ring */
uint32_t rxdesc_ring_end; /* Id of last RxDesc ring */
uint32_t tx_intr_mask; /* tx interrupt mask */
uint32_t rx_intr_mask; /* rx interrupt mask */
uint32_t rxfill_intr_mask; /* Rx fill ring interrupt mask */
uint32_t rxdesc_intr_mask; /* Rx Desc ring interrupt mask */
uint32_t txcmpl_intr_mask; /* Tx Cmpl ring interrupt mask */
uint32_t misc_intr_mask; /* misc interrupt interrupt mask */
};
struct ipq6018_edma_common_info {
struct ipq6018_edma_hw hw;
};
#define MAX_PHY 6
struct ipq6018_eth_dev {
u8 *phy_address;
uint no_of_phys;
uint interface;
uint speed;
uint duplex;
uint sw_configured;
uint mac_unit;
uint mac_ps;
int link_printed;
u32 padding;
struct eth_device *dev;
struct ipq6018_edma_common_info *c_info;
struct phy_ops *ops[MAX_PHY];
const char phy_name[MDIO_NAME_LEN];
} __attribute__ ((aligned(8)));
static inline void* ipq6018_alloc_mem(u32 size)
{
void *p = malloc(size);
if (p != NULL)
memset(p, 0, size);
return p;
}
static inline void* ipq6018_alloc_memalign(u32 size)
{
void *p = memalign(CONFIG_SYS_CACHELINE_SIZE, size);
if (p != NULL)
memset(p, 0, size);
return p;
}
static inline void ipq6018_free_mem(void *ptr)
{
if (ptr)
free(ptr);
}
//extern struct ipq6018_edma_hw ipq6018_edma_hw;
uint32_t ipq6018_edma_reg_read(uint32_t reg_off);
void ipq6018_edma_reg_write(uint32_t reg_off, uint32_t val);
extern int get_eth_mac_address(uchar *enetaddr, uint no_of_macs);
typedef struct {
uint count;
u8 addr[7];
} ipq6018_edma_phy_addr_t;
/* ipq6018 edma Paramaters */
typedef struct {
uint base;
int unit;
uint mac_conn_to_phy;
phy_interface_t phy;
ipq6018_edma_phy_addr_t phy_addr;
char phy_name[MDIO_NAME_LEN];
} ipq6018_edma_board_cfg_t;
extern void ipq6018_ppe_provision_init(void);
extern void ipq6018_speed_clock_set(int port, int speed_clock1, int speed_clock2);
extern void ipq6018_pqsgmii_speed_set(int port, int speed, int status);
extern void ipq6018_uxsgmii_speed_set(int port, int speed, int duplex, int status);
extern void ppe_port_bridge_txmac_set(int port, int status);
extern void ipq6018_10g_r_speed_set(int port, int status);
extern int phy_status_get_from_ppe(int port_id);
extern void ipq6018_ppe_acl_set(int rule_id, int rule_type, int pkt_type, int l4_port_no, int l4_port_mask, int permit, int deny);
extern void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode);
#endif /* ___IPQ6018_EDMA__ */

1323
drivers/net/ipq6018/ipq6018_ppe.c Normal file
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@ -0,0 +1,251 @@
/*
**************************************************************************
* Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
**************************************************************************
*/
#include <common.h>
#include <net.h>
#include <asm-generic/errno.h>
#include <asm/io.h>
#include <malloc.h>
#include <phy.h>
#include <net.h>
#include <miiphy.h>
#define GCC_NSS_PORT1_RX_CMD_RCGR 0x01868020
#define GCC_NSS_PORT1_RX_CFG_RCGR 0x01868024
#define GCC_NSS_PORT1_RX_MISC 0x01868400
#define IPQ6018_PPE_BASE_ADDR 0x3a000000
#define IPQ6018_PPE_REG_SIZE 0x1000000
#define PORT5 5
#define PORT6 6
#define PORT_GMAC_TYPE 1
#define PORT_XGMAC_TYPE 2
struct port_mux_ctrl {
uint32_t port4_pcs_sel:1;
uint32_t port5_pcs_sel:2;
uint32_t port5_gmac_sel:1;
uint32_t port6_pcs_sel:1;
uint32_t port6_gmac_sel:1;
uint32_t _reserved0:26;
};
union port_mux_ctrl_u {
uint32_t val;
struct port_mux_ctrl bf;
};
enum {
TCP_PKT,
UDP_PKT,
};
#define ADPT_ACL_HPPE_IPV4_DIP_RULE 4
#define MAX_RULE 512
struct ipo_rule_reg {
uint32_t rule_field_0:32;
uint32_t rule_field_1:20;
uint32_t fake_mac_header:1;
uint32_t range_en:1;
uint32_t inverse_en:1;
uint32_t rule_type:4;
uint32_t src_type:2;
uint32_t src_0:3;
uint32_t src_1:5;
uint32_t pri:9;
uint32_t res_chain:1;
uint32_t post_routing_en:1;
uint32_t _reserved0:16;
};
union ipo_rule_reg_u {
uint32_t val[3];
struct ipo_rule_reg bf;
};
struct ipo_mask_reg {
uint32_t maskfield_0:32;
uint32_t maskfield_1:21;
uint32_t _reserved0:11;
};
union ipo_mask_reg_u {
uint32_t val[2];
struct ipo_mask_reg bf;
};
struct ipo_action {
uint32_t dest_info_change_en:1;
uint32_t fwd_cmd:2;
uint32_t _reserved0:29;
uint32_t _reserved1:32;
uint32_t _reserved2:32;
uint32_t _reserved3:32;
uint32_t _reserved4:32;
};
union ipo_action_u {
uint32_t val[5];
struct ipo_action bf;
};
#define IPQ6018_PORT_MUX_CTRL 0x10
#define PORT4_PCS_SEL_GMII_FROM_PCS0 1
#define PORT4_PCS_SEL_RGMII 0
#define PORT5_PCS_SEL_RGMII 0
#define PORT5_PCS_SEL_GMII_FROM_PCS0 1
#define PORT5_PCS_SEL_GMII_FROM_PCS1 2
#define PORT5_GMAC_SEL_GMAC 1
#define PORT5_GMAC_SEL_XGMAC 0
#define PORT6_PCS_SEL_RGMII 0
#define PORT6_PCS_SEL_GMII_FROM_PCS2 1
#define PORT6_GMAC_SEL_GMAC 1
#define PORT6_GMAC_SEL_XGMAC 0
#define PORT_PHY_STATUS_ADDRESS 0x44
#define PORT_PHY_STATUS_PORT5_1_OFFSET 8
#define PORT_PHY_STATUS_PORT6_OFFSET 16
#define IPQ6018_PPE_IPE_L3_BASE_ADDR 0x200000
#define IPQ6018_PPE_L3_VP_PORT_TBL_ADDR (IPQ6018_PPE_IPE_L3_BASE_ADDR + 0x1000)
#define IPQ6018_PPE_L3_VP_PORT_TBL_INC 0x10
#define IPQ6018_PPE_QUEUE_MANAGER_BASE_ADDR 0x800000
#define IPQ6018_PPE_UCAST_QUEUE_MAP_TBL_ADDR 0x10000
#define IPQ6018_PPE_UCAST_QUEUE_MAP_TBL_INC 0x10
#define IPQ6018_PPE_QM_UQM_TBL (IPQ6018_PPE_QUEUE_MANAGER_BASE_ADDR +\
IPQ6018_PPE_UCAST_QUEUE_MAP_TBL_ADDR)
#define IPQ6018_PPE_UCAST_PRIORITY_MAP_TBL_ADDR 0x42000
#define IPQ6018_PPE_QM_UPM_TBL (IPQ6018_PPE_QUEUE_MANAGER_BASE_ADDR +\
IPQ6018_PPE_UCAST_PRIORITY_MAP_TBL_ADDR)
#define IPQ6018_PPE_STP_BASE 0x060100
#define IPQ6018_PPE_MAC_ENABLE 0x001000
#define IPQ6018_PPE_MAC_SPEED 0x001004
#define IPQ6018_PPE_MAC_MIB_CTL 0x001034
#define IPQ6018_PPE_TRAFFIC_MANAGER_BASE_ADDR 0x400000
#define IPQ6018_PPE_L0_FLOW_PORT_MAP_TBL_ADDR 0x8000
#define IPQ6018_PPE_L0_FLOW_PORT_MAP_TBL_INC 0x10
#define IPQ6018_PPE_L0_FLOW_PORT_MAP_TBL (IPQ6018_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
IPQ6018_PPE_L0_FLOW_PORT_MAP_TBL_ADDR)
#define IPQ6018_PPE_L0_FLOW_MAP_TBL_ADDR 0x2000
#define IPQ6018_PPE_L0_FLOW_MAP_TBL_INC 0x10
#define IPQ6018_PPE_L0_FLOW_MAP_TBL (IPQ6018_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
IPQ6018_PPE_L0_FLOW_MAP_TBL_ADDR)
#define IPQ6018_PPE_L1_FLOW_PORT_MAP_TBL_ADDR 0x46000
#define IPQ6018_PPE_L1_FLOW_PORT_MAP_TBL_INC 0x10
#define IPQ6018_PPE_L1_FLOW_PORT_MAP_TBL (IPQ6018_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
IPQ6018_PPE_L1_FLOW_PORT_MAP_TBL_ADDR)
#define IPQ6018_PPE_L1_FLOW_MAP_TBL_ADDR 0x40000
#define IPQ6018_PPE_L1_FLOW_MAP_TBL_INC 0x10
#define IPQ6018_PPE_L1_FLOW_MAP_TBL (IPQ6018_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
IPQ6018_PPE_L1_FLOW_MAP_TBL_ADDR)
#define IPQ6018_PPE_L0_C_SP_CFG_TBL_ADDR 0x4000
#define IPQ6018_PPE_L0_C_SP_CFG_TBL (IPQ6018_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
IPQ6018_PPE_L0_C_SP_CFG_TBL_ADDR)
#define IPQ6018_PPE_L1_C_SP_CFG_TBL_ADDR 0x42000
#define IPQ6018_PPE_L1_C_SP_CFG_TBL (IPQ6018_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
IPQ6018_PPE_L1_C_SP_CFG_TBL_ADDR)
#define IPQ6018_PPE_L0_E_SP_CFG_TBL_ADDR 0x6000
#define IPQ6018_PPE_L0_E_SP_CFG_TBL (IPQ6018_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
IPQ6018_PPE_L0_E_SP_CFG_TBL_ADDR)
#define IPQ6018_PPE_L1_E_SP_CFG_TBL_ADDR 0x44000
#define IPQ6018_PPE_L1_E_SP_CFG_TBL (IPQ6018_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
IPQ6018_PPE_L1_E_SP_CFG_TBL_ADDR)
#define IPQ6018_PPE_FPGA_GPIO_BASE_ADDR 0x01008000
#define IPQ6018_PPE_MAC_PORT_MUX_OFFSET 0x10
#define IPQ6018_PPE_FPGA_GPIO_OFFSET 0xc000
#define IPQ6018_PPE_FPGA_SCHED_OFFSET 0x47a000
#define IPQ6018_PPE_TDM_CFG_DEPTH_OFFSET 0xb000
#define IPQ6018_PPE_TDM_SCHED_DEPTH_OFFSET 0x400000
#define IPQ6018_PPE_PORT_BRIDGE_CTRL_OFFSET 0x060300
#define IPQ6018_PPE_TDM_CFG_DEPTH_VAL 0x80000064
#define IPQ6018_PPE_MAC_PORT_MUX_OFFSET_VAL 0x15
#define IPQ6018_PPE_TDM_SCHED_DEPTH_VAL 0x32
#define IPQ6018_PPE_TDM_CFG_VALID 0x20
#define IPQ6018_PPE_TDM_CFG_DIR_INGRESS 0x0
#define IPQ6018_PPE_TDM_CFG_DIR_EGRESS 0x10
#define IPQ6018_PPE_PORT_EDMA 0x0
#define IPQ6018_PPE_PORT_QCOM1 0x1
#define IPQ6018_PPE_PORT_QCOM2 0x2
#define IPQ6018_PPE_PORT_QCOM3 0x3
#define IPQ6018_PPE_PORT_QCOM4 0x4
#define IPQ6018_PPE_PORT_XGMAC1 0x5
#define IPQ6018_PPE_PORT_XGMAC2 0x6
#define IPQ6018_PPE_PORT_CRYPTO1 0x7
#define IPQ6018_PPE_PORT_BRIDGE_CTRL_PROMISC_EN 0x20000
#define IPQ6018_PPE_PORT_BRIDGE_CTRL_TXMAC_EN 0x10000
#define IPQ6018_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP 0x7f00
#define IPQ6018_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN 0x8
#define IPQ6018_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN 0x1
#define IPQ6018_PPE_PORT_EDMA_BITPOS 0x1
#define IPQ6018_PPE_PORT_QCOM1_BITPOS (1 << IPQ6018_PPE_PORT_QCOM1)
#define IPQ6018_PPE_PORT_QCOM2_BITPOS (1 << IPQ6018_PPE_PORT_QCOM2)
#define IPQ6018_PPE_PORT_QCOM3_BITPOS (1 << IPQ6018_PPE_PORT_QCOM3)
#define IPQ6018_PPE_PORT_QCOM4_BITPOS (1 << IPQ6018_PPE_PORT_QCOM4)
#define IPQ6018_PPE_PORT_XGMAC1_BITPOS (1 << IPQ6018_PPE_PORT_XGMAC1)
#define IPQ6018_PPE_PORT_XGMAC2_BITPOS (1 << IPQ6018_PPE_PORT_XGMAC2)
#define IPQ6018_PPE_PORT_CRYPTO1_BITPOS (1 << IPQ6018_PPE_PORT_CRYPTO1)
#define PPE_SWITCH_NSS_SWITCH_XGMAC0 0x3000
#define NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION 0x4000
#define USS (1 << 31)
#define SS(i) (i << 29)
#define JD (1 << 16)
#define TE (1 << 0)
#define NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION 0x4000
#define MAC_RX_CONFIGURATION_ADDRESS 0x4
#define RE (1 << 0)
#define ACS (1 << 1)
#define CST (1 << 2)
#define MAC_PACKET_FILTER_INC 0x4000
#define MAC_PACKET_FILTER_ADDRESS 0x8
#define XGMAC_SPEED_SELECT_10000M 0
#define XGMAC_SPEED_SELECT_5000M 1
#define XGMAC_SPEED_SELECT_2500M 2
#define XGMAC_SPEED_SELECT_1000M 3
#define IPE_L2_BASE_ADDR 0x060000
#define PORT_BRIDGE_CTRL_ADDRESS 0x300
#define PORT_BRIDGE_CTRL_INC 0x4
#define TX_MAC_EN (1 << 16)
#define IPO_CSR_BASE_ADDR 0x0b0000
#define IPO_RULE_REG_ADDRESS 0x0
#define IPO_RULE_REG_INC 0x10
#define IPO_MASK_REG_ADDRESS 0x2000
#define IPO_MASK_REG_INC 0x10
#define IPO_ACTION_ADDRESS 0x8000
#define IPO_ACTION_INC 0x20

358
drivers/net/ipq6018/ipq6018_uniphy.c Normal file
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@ -0,0 +1,358 @@
/*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <net.h>
#include <asm-generic/errno.h>
#include <asm/io.h>
#include <malloc.h>
#include <phy.h>
#include <net.h>
#include <miiphy.h>
#include <asm/arch-ipq6018/edma_regs.h>
#include "ipq6018_edma.h"
#include "ipq6018_uniphy.h"
#include "ipq_phy.h"
extern int ipq_mdio_write(int mii_id,
int regnum, u16 value);
extern int ipq_mdio_read(int mii_id,
int regnum, ushort *data);
extern void qca8075_phy_serdes_reset(u32 phy_id);
void csr1_write(int phy_id, int addr, int value)
{
int addr_h, addr_l, ahb_h, ahb_l, phy;
phy=phy_id<<(0x10);
addr_h=(addr&0xffffff)>>8;
addr_l=((addr&0xff)<<2)|(0x20<<(0xa));
ahb_l=(addr_l&0xffff)|(0x7A00000|phy);
ahb_h=(0x7A083FC|phy);
writel(addr_h,ahb_h);
writel(value,ahb_l);
}
int csr1_read(int phy_id, int addr )
{
int addr_h ,addr_l,ahb_h, ahb_l, phy;
phy=phy_id<<(0x10);
addr_h=(addr&0xffffff)>>8;
addr_l=((addr&0xff)<<2)|(0x20<<(0xa));
ahb_l=(addr_l&0xffff)|(0x7A00000|phy);
ahb_h=(0x7A083FC|phy);
writel(addr_h, ahb_h);
return readl(ahb_l);
}
static int ppe_uniphy_calibration(uint32_t uniphy_index)
{
int retries = 100, calibration_done = 0;
uint32_t reg_value = 0;
while(calibration_done != UNIPHY_CALIBRATION_DONE) {
mdelay(1);
if (retries-- == 0) {
printf("uniphy callibration time out!\n");
return -1;
}
reg_value = readl(PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ PPE_UNIPHY_OFFSET_CALIB_4);
calibration_done = (reg_value >> 0x7) & 0x1;
}
return 0;
}
static void ppe_gcc_uniphy_xpcs_reset(uint32_t uniphy_index, bool enable)
{
uint32_t reg_value;
if(enable)
reg_value = GCC_UNIPHY_USXGMII_XPCS_RESET;
else
reg_value = GCC_UNIPHY_USXGMII_XPCS_RELEASE_RESET;
writel(reg_value, GCC_UNIPHY0_MISC + (uniphy_index * GCC_UNIPHY_REG_INC));
}
static void ppe_gcc_uniphy_soft_reset(uint32_t uniphy_index)
{
uint32_t reg_value;
reg_value = readl(GCC_UNIPHY0_MISC + (uniphy_index * GCC_UNIPHY_REG_INC));
if (uniphy_index == PPE_UNIPHY_INSTANCE0)
reg_value |= GCC_UNIPHY_PSGMII_SOFT_RESET;
else
reg_value = GCC_UNIPHY_USXGMII_SOFT_RESET;
writel(reg_value, GCC_UNIPHY0_MISC + (uniphy_index * GCC_UNIPHY_REG_INC));
udelay(500);
if (uniphy_index == PPE_UNIPHY_INSTANCE0)
reg_value &= ~GCC_UNIPHY_PSGMII_SOFT_RESET;
else
reg_value = GCC_UNIPHY_USXGMII_XPCS_RESET;
writel(reg_value, GCC_UNIPHY0_MISC + (uniphy_index * GCC_UNIPHY_REG_INC));
}
static void ppe_uniphy_psgmii_mode_set(uint32_t uniphy_index)
{
ppe_gcc_uniphy_xpcs_reset(uniphy_index, true);
writel(0x220, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ PPE_UNIPHY_MODE_CONTROL);
ppe_gcc_uniphy_soft_reset(uniphy_index);
ppe_uniphy_calibration(uniphy_index);
qca8075_phy_serdes_reset(0);
}
static void ppe_uniphy_qsgmii_mode_set(uint32_t uniphy_index)
{
ppe_gcc_uniphy_xpcs_reset(uniphy_index, true);
writel(0x120, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ PPE_UNIPHY_MODE_CONTROL);
ppe_gcc_uniphy_soft_reset(uniphy_index);
}
static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t channel)
{
uint32_t reg_value;
writel(UNIPHY_MISC2_REG_SGMII_MODE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET);
writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET);
udelay(500);
writel(UNIPHY_PLL_RESET_REG_DEFAULT_VALUE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET);
ppe_gcc_uniphy_xpcs_reset(uniphy_index, true);
reg_value = readl( PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ PPE_UNIPHY_MODE_CONTROL);
reg_value &= ~(UNIPHY_CH0_ATHR_CSCO_MODE_25M | UNIPHY_CH0_PSGMII_QSGMII);
if (uniphy_index == PPE_UNIPHY_INSTANCE0) {
reg_value &= ~UNIPHY_SG_MODE;
if (channel == 0) {
reg_value &= ~UNIPHY_CH1_CH0_SGMII;
reg_value &= ~UNIPHY_CH4_CH1_0_SGMII;
} else if (channel == 1) {
reg_value |= UNIPHY_CH1_CH0_SGMII;
reg_value &= ~UNIPHY_CH4_CH1_0_SGMII;
} else if (channel == 4) {
reg_value &= ~UNIPHY_CH1_CH0_SGMII;
reg_value |= UNIPHY_CH4_CH1_0_SGMII;
}
} else {
reg_value &= ~UNIPHY_SG_PLUS_MODE;
reg_value |= UNIPHY_SG_MODE;
}
writel(reg_value, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ PPE_UNIPHY_MODE_CONTROL);
ppe_gcc_uniphy_soft_reset(uniphy_index);
}
static void ppe_uniphy_sgmii_plus_mode_set(uint32_t uniphy_index)
{
writel(UNIPHY_MISC2_REG_SGMII_PLUS_MODE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET);
writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET);
udelay(500);
writel(UNIPHY_PLL_RESET_REG_DEFAULT_VALUE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET);
ppe_gcc_uniphy_xpcs_reset(uniphy_index, true);
writel(0x800, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ PPE_UNIPHY_MODE_CONTROL);
ppe_gcc_uniphy_soft_reset(uniphy_index);
ppe_uniphy_calibration(uniphy_index);
}
static int ppe_uniphy_10g_r_linkup(uint32_t uniphy_index)
{
uint32_t reg_value = 0;
uint32_t retries = 100, linkup = 0;
while (linkup != UNIPHY_10GR_LINKUP) {
mdelay(1);
if (retries-- == 0)
return -1;
reg_value = csr1_read(uniphy_index, SR_XS_PCS_KR_STS1_ADDRESS);
linkup = (reg_value >> 12) & UNIPHY_10GR_LINKUP;
}
mdelay(10);
return 0;
}
static void ppe_uniphy_10g_r_mode_set(uint32_t uniphy_index)
{
ppe_gcc_uniphy_xpcs_reset(uniphy_index, true);
writel(0x1021, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ PPE_UNIPHY_MODE_CONTROL);
writel(0x1C0, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ UNIPHY_INSTANCE_LINK_DETECT);
ppe_gcc_uniphy_soft_reset(uniphy_index);
ppe_uniphy_calibration(uniphy_index);
ppe_gcc_uniphy_xpcs_reset(uniphy_index, false);
}
static void ppe_uniphy_usxgmii_mode_set(uint32_t uniphy_index)
{
uint32_t reg_value = 0;
writel(UNIPHY_MISC2_REG_VALUE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET);
writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET);
mdelay(500);
writel(UNIPHY_PLL_RESET_REG_DEFAULT_VALUE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET);
mdelay(500);
ppe_gcc_uniphy_xpcs_reset(uniphy_index, true);
writel(0x1021, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ PPE_UNIPHY_MODE_CONTROL);
ppe_gcc_uniphy_soft_reset(uniphy_index);
ppe_uniphy_calibration(uniphy_index);
ppe_gcc_uniphy_xpcs_reset(uniphy_index, false);
ppe_uniphy_10g_r_linkup(uniphy_index);
reg_value = csr1_read(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS);
reg_value |= USXG_EN;
csr1_write(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS, reg_value);
reg_value = csr1_read(uniphy_index, VR_MII_AN_CTRL_ADDRESS);
reg_value |= MII_AN_INTR_EN;
reg_value |= MII_CTRL;
csr1_write(uniphy_index, VR_MII_AN_CTRL_ADDRESS, reg_value);
reg_value = csr1_read(uniphy_index, SR_MII_CTRL_ADDRESS);
reg_value |= AN_ENABLE;
reg_value &= ~SS5;
reg_value |= SS6 | SS13 | DUPLEX_MODE;
csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value);
if (uniphy_index == PPE_UNIPHY_INSTANCE2);
ipq_mdio_write(0x7, ((1<<30) | (4<<16) | 0xc441), 8);
}
void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode)
{
switch(mode) {
case PORT_WRAPPER_PSGMII:
ppe_uniphy_psgmii_mode_set(uniphy_index);
break;
case PORT_WRAPPER_QSGMII:
ppe_uniphy_qsgmii_mode_set(uniphy_index);
break;
case PORT_WRAPPER_SGMII0_RGMII4:
ppe_uniphy_sgmii_mode_set(uniphy_index, 0);
break;
case PORT_WRAPPER_SGMII1_RGMII4:
ppe_uniphy_sgmii_mode_set(uniphy_index, 1);
break;
case PORT_WRAPPER_SGMII4_RGMII4:
ppe_uniphy_sgmii_mode_set(uniphy_index, 4);
break;
case PORT_WRAPPER_SGMII_PLUS:
ppe_uniphy_sgmii_plus_mode_set(uniphy_index);
break;
case PORT_WRAPPER_USXGMII:
ppe_uniphy_usxgmii_mode_set(uniphy_index);
break;
case PORT_WRAPPER_10GBASE_R:
ppe_uniphy_10g_r_mode_set(uniphy_index);
break;
default:
break;
}
}
void ppe_uniphy_usxgmii_autoneg_completed(uint32_t uniphy_index)
{
uint32_t autoneg_complete = 0, retries = 100;
uint32_t reg_value = 0;
while (autoneg_complete != 0x1) {
mdelay(1);
if (retries-- == 0)
{
return;
}
reg_value = csr1_read(uniphy_index, VR_MII_AN_INTR_STS);
autoneg_complete = reg_value & 0x1;
}
reg_value &= ~CL37_ANCMPLT_INTR;
csr1_write(uniphy_index, VR_MII_AN_INTR_STS, reg_value);
}
void ppe_uniphy_usxgmii_speed_set(uint32_t uniphy_index, int speed)
{
uint32_t reg_value = 0;
reg_value = csr1_read(uniphy_index, SR_MII_CTRL_ADDRESS);
reg_value |= DUPLEX_MODE;
switch(speed) {
case 0:
reg_value &=~SS5;
reg_value &=~SS6;
reg_value &=~SS13;
break;
case 1:
reg_value &=~SS5;
reg_value &=~SS6;
reg_value |=SS13;
break;
case 2:
reg_value &=~SS5;
reg_value |=SS6;
reg_value &=~SS13;
break;
case 3:
reg_value &=~SS5;
reg_value |=SS6;
reg_value |=SS13;
break;
case 4:
reg_value |=SS5;
reg_value &=~SS6;
reg_value &=~SS13;
break;
case 5:
reg_value |=SS5;
reg_value &=~SS6;
reg_value |=SS13;
break;
}
csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value);
}
void ppe_uniphy_usxgmii_duplex_set(uint32_t uniphy_index, int duplex)
{
uint32_t reg_value = 0;
reg_value = csr1_read(uniphy_index, SR_MII_CTRL_ADDRESS);
if (duplex & 0x1)
reg_value |= DUPLEX_MODE;
else
reg_value &= ~DUPLEX_MODE;
csr1_write(uniphy_index, SR_MII_CTRL_ADDRESS, reg_value);
}
void ppe_uniphy_usxgmii_port_reset(uint32_t uniphy_index)
{
uint32_t reg_value = 0;
reg_value = csr1_read(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS);
reg_value |= USRA_RST;
csr1_write(uniphy_index, VR_XS_PCS_DIG_CTRL1_ADDRESS, reg_value);
}

78
drivers/net/ipq6018/ipq6018_uniphy.h Normal file
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@ -0,0 +1,78 @@
/*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#define PPE_UNIPHY_INSTANCE0 0
#define PPE_UNIPHY_INSTANCE1 1
#define PPE_UNIPHY_INSTANCE2 2
#define GCC_UNIPHY0_MISC 0x01856004
#define GCC_UNIPHY_REG_INC 0x100
#define GCC_UNIPHY_USXGMII_XPCS_RESET 0x4
#define GCC_UNIPHY_USXGMII_XPCS_RELEASE_RESET 0x0
#define PPE_UNIPHY_OFFSET_CALIB_4 0x1E0
#define UNIPHY_CALIBRATION_DONE 0x1
#define GCC_UNIPHY_PSGMII_SOFT_RESET 0x3ff2
#define GCC_UNIPHY_USXGMII_SOFT_RESET 0x36
#define PPE_UNIPHY_BASE 0X07A00000
#define PPE_UNIPHY_REG_INC 0x10000
#define PPE_UNIPHY_MODE_CONTROL 0x46C
#define UNIPHY_XPCS_MODE (1 << 12)
#define UNIPHY_SG_PLUS_MODE (1 << 11)
#define UNIPHY_SG_MODE (1 << 10)
#define UNIPHY_CH0_PSGMII_QSGMII (1 << 9)
#define UNIPHY_CH0_QSGMII_SGMII (1 << 8)
#define UNIPHY_CH4_CH1_0_SGMII (1 << 2)
#define UNIPHY_CH1_CH0_SGMII (1 << 1)
#define UNIPHY_CH0_ATHR_CSCO_MODE_25M (1 << 0)
#define UNIPHY_INSTANCE_LINK_DETECT 0x570
#define UNIPHY_MISC2_REG_OFFSET 0x218
#define UNIPHY_MISC2_REG_SGMII_MODE 0x30
#define UNIPHY_MISC2_REG_SGMII_PLUS_MODE 0x50
#define UNIPHY_MISC2_REG_VALUE 0x70
#define UNIPHY_PLL_RESET_REG_OFFSET 0x780
#define UNIPHY_PLL_RESET_REG_VALUE 0x02bf
#define UNIPHY_PLL_RESET_REG_DEFAULT_VALUE 0x02ff
#define SR_XS_PCS_KR_STS1_ADDRESS 0x30020
#define UNIPHY_10GR_LINKUP 0x1
#define VR_XS_PCS_DIG_CTRL1_ADDRESS 0x38000
#define USXG_EN (1 << 9)
#define USRA_RST (1 << 10)
#define VR_MII_AN_CTRL_ADDRESS 0x1f8001
#define MII_AN_INTR_EN (1 << 0)
#define MII_CTRL (1 << 8)
#define SR_MII_CTRL_ADDRESS 0x1f0000
#define AN_ENABLE (1 << 12)
#define SS5 (1 << 5)
#define SS6 (1 << 6)
#define SS13 (1 << 13)
#define DUPLEX_MODE (1 << 8)
#define VR_MII_AN_INTR_STS 0x1f8002
#define CL37_ANCMPLT_INTR (1 << 0)
void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode);
void ppe_uniphy_usxgmii_port_reset(uint32_t uniphy_index);
void ppe_uniphy_usxgmii_duplex_set(uint32_t uniphy_index, int duplex);
void ppe_uniphy_usxgmii_speed_set(uint32_t uniphy_index, int speed);
void ppe_uniphy_usxgmii_autoneg_completed(uint32_t uniphy_index);

21
include/configs/ipq6018.h
View file

@ -27,6 +27,8 @@
#define CONFIG_SYS_VSNPRINTF
#define CONFIG_IPQ_NO_RELOC
#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20)
#define CONFIG_IPQ6018_UART
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SKIP_LOWLEVEL_INIT
@ -287,6 +289,25 @@ extern loff_t board_env_size;
#define TZ_VERSION 1
#define RPM_VERSION 3
#endif
#define CONFIG_IPQ6018_EDMA 1
#define CONFIG_IPQ6018_BRIDGED_MODE 1
#define CONFIG_NET_RETRY_COUNT 5
#define CONFIG_SYS_RX_ETH_BUFFER 16
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_MII
#define CONFIG_CMD_MII
#define CONFIG_IPADDR 192.168.10.10
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.10.1
#define CONFIG_CMD_TFTPPUT
#define CONFIG_IPQ_MDIO 1
#define CONFIG_QCA8075_PHY 1
#define CONFIG_QCA8033_PHY 1
#define CONFIG_QCA8081_PHY 1
#define CONFIG_IPQ_ETH_INIT_DEFER
/* L1 cache line size is 64 bytes, L2 cache line size is 128 bytes
* Cache flush and invalidation based on L1 cache, so the cache line
* size is configured to 64 */