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ipq40xx: make sure that the cache flush instruction gets complete

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Adding the DSB/ISB instructions in the dcache flush functions
 to make sure that the cache flush instruction gets completed
before another instruction executes.

Change-Id: I0bc2222cb040a96cc7413586b9131904bd5d1167
Signed-off-by: sameeruddin shaik <samesh@codeaurora.org>
This commit is contained in:
sameeruddin shaik 2019-03-08 10:41:36 +05:30
parent 90f4f9344b
commit 441cf444f8
1 changed files with 10 additions and 0 deletions
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10
arch/arm/cpu/armv7/cache_v7.c
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@ -118,6 +118,8 @@ static void v7_inval_dcache_level_setway(void)
}
/* DSB to make sure the operation is complete */
DSB;
/* Full system ISB - make sure the instruction stream sees it */
ISB;
}
static void v7_clean_inval_dcache_level_setway(void)
@ -142,6 +144,8 @@ static void v7_clean_inval_dcache_level_setway(void)
}
/* DSB to make sure the operation is complete */
DSB;
/* Full system ISB - make sure the instruction stream sees it */
ISB;
}
static void v7_maint_dcache_level_setway(void)
@ -173,6 +177,8 @@ static void v7_maint_dcache_level_setway(void)
} else if (c1.operation == ARMV7_DCACHE_CLEAN_INVAL_ALL) {
v7_clean_inval_dcache_level_setway();
}
DSB;
ISB;
}
static void v7_maint_dcache_all(void)
@ -188,6 +194,8 @@ static void v7_maint_dcache_all(void)
v7_maint_dcache_level_setway();
c1.level_start_bit += 3;
}
DSB;
ISB;
}
static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len)
@ -259,6 +267,8 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
/* DSB to make sure the operation is complete */
DSB;
/* Full system ISB - make sure the instruction stream sees it */
ISB;
}
/* Invalidate TLB */