mirror/u-boot-2016
1
0
Fork 0
mirror of https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git synced 2026-03-10 11:17:18 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

dts: ipq6018: Configuring spi nor and nand gpio's in common soc file

Browse source 
Change-Id: I6d7dce08765a5ada48362117dec79e5b558807ca
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
This commit is contained in:
Antony Arun T 2019-04-03 11:33:33 +05:30
parent 58e4e2036b
commit 3210ceb503
1 changed files with 151 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

151
arch/arm/dts/ipq6018-soc.dtsi
View file

@ -65,6 +65,157 @@
reg = <0x7000000 0xcd00>;
};
spi {
status = "ok";
compatible = "qcom,spi-qup-v2.7.0";
wr_pipe_0 = <12>;
rd_pipe_0 = <13>;
spi_gpio {
gpio1 {
gpio = <38>;
func = <3>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio2 {
gpio = <39>;
func = <3>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio3 {
gpio = <40>;
func = <2>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio4 {
gpio = <41>;
func = <2>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
oe = <GPIO_OE_DISABLE>;
};
};
};
nand: nand-controller@79B0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,qpic-nand.1.5.20";
reg = <0x79B0000 0x10000>;
nand_gpio {
gpio1 {
gpio = <1>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio2 {
gpio = <3>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio3 {
gpio = <4>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio4 {
gpio = <5>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio5 {
gpio = <6>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio6 {
gpio = <7>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio7 {
gpio = <8>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio8 {
gpio = <10>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_8MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio9 {
gpio = <11>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio10 {
gpio = <12>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio11 {
gpio = <13>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio12 {
gpio = <14>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio13 {
gpio = <15>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_DISABLE>;
};
gpio14 {
gpio = <17>;
func = <1>;
pull = <GPIO_PULL_DOWN>;
drvstr = <GPIO_2MA>;
oe = <GPIO_OE_DISABLE>;
};
};
};
pci@20000000 {
compatible = "qcom,ipq6018-pcie";
#address-cells = <1>;