This change will fix memory leak problem in serial training.
For serial tarining we are allocating memory to hold the training
pattern buf. For any failure we are freeing the buffer but due to
wrong lavel used memory was not getting freed due to this memory leak
problem is happening.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I35ffd27df9b24ea53aed9e9f0623d8890ba66f06
This change fix Access violation created by APPS
master by accessing QPIC_XPU issue due to accessing
QPIC_QSPI_MSTR_CONFIG & QPIC_NAND_FLASH_SPI_CFG registers
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ibb840db12359eea01823dd7732fcb1ac1e7b8967
This change will fix erase address configuration for QSPI
nand devices whose density is beyond 128MiB.
To erase a block as per datasheet of serial nand device
page row address <5:0> and the Block row address <16:6>.
In code we are forming directly pages address starting
from <16:0> i.e 17-bit address. Currently we are configuring
address_0 and address_1 register as follws.
addr0 = (page << 16) and addr1 = 0x0;
This logic will work if device size upto 128MiB, but if device
size beyond 128MiB then this logic will fail becasue upper most bit
will go out of add0 register.
Fixing this by changing address configuration logic for erase block.
addr0 = (page << 16) addr1 = (page >> 16) & 0xffff;
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I4950bb611780257629491ffbb42c91fcfedebc58
This change will define qspi_debug macro to print
debug messages.
Change-Id: I49c5278f63fa53dc5b2237aeb9bfef97990ecc86
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This change will enable config for serial training.
This change also fix the the logic to get most appropriate phase
out of passed phase.
This change also add support to read serial training offset from
partition table. Also patching freqency value & phase value to kernel.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: Ibb4a5cd80f16605e8e91bdf6a0c6c484edff1735
This change will fix NULL pointer dereference while reading
from spi nand flash in oobbuf.
The multipage read features is only to read with ecc for
raw read/write the the access is page wise due to mtd layer
will request only one page at a time. So don't increment oobbuf
for every page while reading if already bitflips are present in spi
nand flash. if so data abort will happen due to NULL pointer
dereference.
error:
NAND read: device 0 offset 0x4480000, size 0x1000
data abort
pc : [<4a9515ec>] lr : [<44000e18>]
reloc pc : [<4a9515ec>] lr : [<44000e18>]
sp : 4a77f6f4 ip : bbfff3dc fp : 4a783510
r10: 4a97bb40 r9 : 4a77feb0 r8 : 44000e0c
r7 : 4a97ca2c r6 : 0000000f r5 : 00000004 r4 : 00000003
r3 : ffffffff r2 : 000001f4 r1 : 000000ff r0 : 44000e0c
Flags: nzCv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
resetting ...
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I435f65183b56ceef64bad7d0df7ffebe02175a66
This change will fix serial training logic and enable
config to enable default qpic_io_macro clock @ 80MHz with
default phase delay valu 4 for all qspi serial line.
This change also fix the delay issue while writing to qpic
register via bam.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I345f736fdae9d48b6da0115ca7a8519b43fe9efd
This change will add support to write some ops group register via
BAM to avoid xPU error.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I65ea875f783b7254f01cb3cf43eb43295caa4ed9
This change will add support for serial training in
QPIC.
Due to different PNR and PCB delays, serial read data
can come with different delays to QPIC. At high frequency
operations Rx clock should be adjusted according to delays
so that Rx Data can be captured correctly. CLK_CNTR_INIT_VAL_VEC
in NAND_FLASH_SPI_CFG register is a 12-bit vector which is divided
in 4 parts of 3 bits each representing delay of 4 serial input data
lines. Bit [2:0] corresponds to qspi_miso[0], bit [5:3] corresponds
to qspi_miso[1], bit [8:6] corresponds to qspi_miso[2] and bit [11:9]
corresponds to qspi_miso[3]. Delay of each qspi_miso line can be set
from 0 to 7.
For serial training the following rule should be followd.
1) SW should write a page with any known pattern in flash at lower
frequency.
2) Set the CLK_CNTR_INIT_VAL_VEC for qspi_miso[0] line.
3) Read that page repetitively in high frequency mode until it
gets data accurately.
4) Repeat above steps for other qspi_miso lines.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: If622809efff55fb2abe60f409a590abd5313741b
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This change will enable page_scope_read & multipage_read support for
QPIC.
QPIC version 2.0 onwards , QPIC support page_scope_read &
multipage_read command to enhance the read performance.
In normal page read command SW is needed to write EXEC_CMD register
for each Code word and collect any Status related to that CW before
issueing EXEC_CMD for next CW.
For page_scope read command SW is required to issue EXEC_CMD
only once for a page. Controller HW takes care of Codeword specific
details and automatically returns status associated with each CW to
BAM pipe, dedicated for status deposition.
enabling all bits in NAND_AUTO_STATUS_EN will require 4 data
descriptors of 24 bytes each. This will publish all NANDc status
registers in system memory.
For multipage_read command SW is required to issue EXEC_CMD only
once for all the pages which configured in QPIC_NAND_MULTI_PAGE_CMD
register.
All interrupts will be operational and valid in these modes.
To check the status for each codeword, it is not possible to access
the status registers while the read command is operational in
page_scope & multi_page read modes. Hence, another feature to publish the
status data (for all NAND status registers) by programming the
NAND_AUTO_STATUS_EN register.
For serial NAND:
Read command for page_scope_read = 0x78800032 (QPIC_NAND_FLASH_CMD)
Read command for multi_page_read = 0x78400032 (QPIC_NAND_FLASH_CMD)
For Parallel NAND:
Read command for page_scope_read = 0x00800032 (QPIC_NAND_FLASH_CMD)
Read command for multi_page_read = 0x00400032 (QPIC_NAND_FLASH_CMD)
Now we fixed maximum data bytes read in one go 128KiB(2KiB page),
256KiB (4KiB page), 512 KiB (8kiB page), because from upper layer
we are getting more than 128KiB data bytes request in one go. if so
just changing the value of "MAX_MULTI_PAGE" macro will increase the
maximum data bytes in one go.
Change-Id: I48eea51ff8f5f79f3490d8a538c295ecc3eeee19
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Since nand configuration is fixed across all HK boards,
removing the nand gpio_entries from device tree and
adding static board param entries. This helps reduce
image footprint and opens up space for new board support.
Change-Id: I89bc11165a6cdfcdb3b4650a73cbeea17895f991
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
This change will add support for serial nand.
QPIC-2.1.1 supports parallel nand as well as serial nand.
QPIC will operate either in parallel configuration or
serial nand. Both can't work together.
This change will support initially four serial nand parts.
MT29F1G01ABBFDWB-IT (Micron-0x2C,0x15, 2K + 128)
GD5F1GQ4RE9IG (Giga Device-0xC8,0xC1, 2K + 128)
GD5F2GQ5REYIH (Giga Device-0xC8,0x22, 2K + 64)
GD5F1GQ4RE9IH (Giga Device-0xC8, 0xC9, 2K + 64)
Device Internal ECC is disabled for all three devices. This change will
enabele QPIC ECC engine.
For MT29F1G01ABBFDWB-IT 4-bit ECC as well 8-bit ECC will be supported.
For GD5F1GQ4RE9IG 4-bit ECC as well 8-bit ECC will be supported.
For GD5F2GQ5REYIH only 4-bit ECC will be supported due to 64-bytes spare.
For GD5F1GQ4RE9IH only 4-bit ECC will be supported due to 64-bytes spare.
Change-Id: I3f38f9c76b7bb235bb335a481fbc42ae1bd00395
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This patch fixes the nand flash size access issue
found in flash with two logical units
Change-Id: Ifcbaa40709c4ac5d508b629fcc6cf7006f167628
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
This change will read entire ONFI parameter page. This will helpful
while validating new ONFI AVL part.
To read entire ONFI parameter page data structure use command:
"#nand onfipara".
Change-Id: Icea80fce6900716871d8c82a2d1ac0c00531af98
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Currently, the nand driver expects the start address to be page
aligned. This patch adds the support for reading data from
non-page aligned start address by using intermediate buffer.
1. Determine the number of pages with start address and
length.
2. Do the full page read for all the pages. For first page,
check the start address and determine the column. If column is
non-zero then use the intermediate buffer for page data and copy
the required number of bytes from this intermediate buffer to
actual buffer.
Change-Id: I05a4b98547c83f785096027596cedd83a283edd8
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Currently NAND_CTRL register write generates error.
Register writes to operational registers should always be done
through command descriptors if BAM_MODE is already enabled.
For NAND boot, bootloader already enables BAM_MODE so read the
NAND_CTRL register value and write only if BAM_MODE is not set.
Change-Id: Iabc3e06dc7d8d8b36cdf35907217e1c4d7cc960a
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
If nand id table has specified oobsize then use the same.
Change-Id: I58b19f8f9989c7332d103b83b6920d5b59b29a13
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Following error is coming during UBI mount for non ONFI nand
device since mtd->writebufsize is coming as zero
ubi0: attaching mtd2
UBI init error 22
The mtd->writebufsize is being assigned currently for ONFI
devices only so move this assigment to common place.
Change-Id: Idd22800dd65035952c1afd07ba375a28ffcf76ad
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
The ONFI NAND device specifies the required ECC correction in its
param page but for non ONFI device, we don't have such info.
The QPIC NAND contoller can use 8 bit ECC if the chip has required
number of spare bytes. This patch calculates the minimum required
spare bytes for using 8 bit ECC and select the same, if non ONFI
device has required number of spare bytes otherwise 4 bit ECC
will be used.
Change-Id: If7c718f4288eee16857171335897e3209a05fd0b
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
This patch adds the support on nand driver to work
when dcache is on.
flush_dcache_range will do both clean and invalidate.
To avoid any data loss when an un-aligned buffer used
in RX path, before giving buffer to bam and after bam
updates the data in buffer, buffer will be flushed.
Change-Id: Ib38d68726efe1692ae94c2be1af61cf29d1c2e50
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Some of the newer nand parts can have bit flips in an erased
page due to the process technology used. In this case, qpic
nand controller is not able to identify that page as an erased
page. In case of bitflips, the ECC engine tries to correct the
data and then it generates the uncorrectable error. Now, this
data is not equal to original raw data.
Following logic is being added to identify the erased
codeword bitflips.
1. Maintain the bitmasks for the codewords which generated
uncorrectable error.
2. Read the raw data again in temp buffer and count the
number of zeros. Since spare bytes are unused in ECC layout and
won’t affect ECC correctability so no need to count number of
zero in spare bytes.
3. If the number of zero is below ECC correctability then it
can be treated as erased CW. In this case, make all the data/oob
of actual user buffers as 0xff.
Change-Id: Ie0427c6802e2e41234137e0fbbf51c5a50a35946
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
This patch does minor code reorganization to store spare, ecc and
bbm bytes in nand device structure which will be useful in
subsequent patches.
Change-Id: Id44c53e204a874569968764798c346a609695acf
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Following are the major issues in current implementation for
checking the read errors
1. For checking the erased CW, NAND_ERASED_CW_DETECT_STATUS
is being read inside qpic_nand_check_status. The
qpic_nand_check_status will be called after complete page read
so reading status register won’t help in getting the register
value after each CW reads.
2. The mtd layer expects the driver to return non-negative
integer representing the maximum number of bitflips that were
corrected on any one ecc region. The mtd layer takes care of
returning EUCLEAN based on returned number.
3. mtd->ecc_stats is only applicable when ECC engine is
doing ECC correction. For raw reads, the stats should not be
incremented.
Now the changes have been done to reorganize the error handling
1. schedule the NAND_ERASED_CW_DETECT_STATUS reading after
every CW read and check the same if ECC engine generates
uncorrectable error.
2. For raw read, the ECC engine will never generate the
uncorrectable error or erased CW so check only
NAND_FLASH_STATUS.
3. The qpic_nand_read_oob should return the maximum number
of bitflips that were corrected on any one ecc region so
introduce the max_bitflips for maintaining the same.
4. The read should return the complete data in case of
BADMSG so move the BADMSG check in the main read function.
Change-Id: Ibef56294ace00d7cd67b501f623fb1d3aeb2c6ec
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
1. ecc strength can be assigned in mtd structure itself so
remove the ecc_width from qpic nand dev structure
2. Initialize bitflip_threshold with 3*4 of ecc strength so
that MTD layer will return EUCLEAN if number of ecc correction
are more than bitflip_threshold.
Change-Id: Ieafd1957b89a05f9dd0fdfe829712d8891bd6a48
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
NANDC_RESULT_BAD_PAGE is not being returned by any operation, so
it can be removed.
Change-Id: Ia90e4e6b7ef7577d069d312d51083b50f49bf980
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Reset command must be the first command issued to all
targets after the NAND flash device is powered on.
Change-Id: I617dc5b0ad8d72705dcf20f1cb554134b166e533
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
NAND_CMD_PRG_PAGE_ALL uses the spare data from buffer itself
which is not applicable. The spare area in NAND page for
QPIC are dummy bytes so 0xff should be written to these
spare area. NAND_CMD_PRG_PAGE does the same thing and HLOS
driver uses this command for all page program
operations. The actual spare data is being written along
with every codeword since the codewords size is 516 in which
512 bytes are user data and 4 bytes are spare data.
Change-Id: I5651caf5ea95f046570e8318f59e140398869ece
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
1. This driver is directly being registered with MTD
layer so for OOB operations, the device OOB size will be
passed. QPIC can’t handle the complete OOB so calculate QPIC
supported OOB size and overwrite the device OOB size with
QPIC supported OOB size.
2. OOB available calculation was wrong. The available OOB’s are
4 bytes per codeword.
3. Raw configuration codeword size was hardcoded to 528 while 8
bit ECC codeword size is 532.
Change-Id: Idc118e2fdd9882758da9dc6b1e977e04697a5640
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
The QPIC XFER STEPS will not be configured in non NAND boot
mode and the data transfer speed will be very slow. Now this
patch reads the timing parameter from ONFI page and configures
the NAND XFER STEPS registers for highest supported ONFI mode.
For NON ONFI device, it will configure to default mode.
Change-Id: I2daf4a92255307efc53db9bb7fe2f02e8c00c3fa
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
As the U-boot source is going to be common between ARM and MIPS
architecture , it is required to pick only the files specific
to the respective architectures during the build.
So, move the qca arm target specific common files to another
sub level by specifying the ARCH arm.
Change-Id: I06b538834109981f21fef6270bfb8e437a2f5a7e
Signed-off-by: Prabhu Jayakumar <pjayak@codeaurora.org>
The writebufsize is introduced in mtd struct for the ubi fastmap
support.
This is not initialized in the qpic nand driver which leads to ubi
error.
Fixed the following ubi error.
bad write buffer size 0 for 2048 min. I/O unit
UBI init error 22
Change-Id: Ie523affe2d202f0e7b3e17dc4ecec19f7c02de27
Signed-off-by: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
Fixed warnings for both ipq807x and ipq40xx
builds.
Change-Id: I69accebf525ee52f470335a14474378f5e7f65b0
Signed-off-by: Saravanan Jaganathan <sjaganat@codeaurora.org>
