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driver: nand: qpic_nand: Fix Erase address configuration.

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This change will fix erase address configuration for QSPI
nand devices whose density is beyond 128MiB.

To erase a block as per datasheet of serial nand device
page row address <5:0> and the Block row address <16:6>.

In code we are forming directly pages address starting
from <16:0> i.e 17-bit address. Currently we are configuring
address_0 and address_1 register as follws.

addr0 = (page << 16) and addr1 = 0x0;

This logic will work if device size upto 128MiB, but if device
size beyond 128MiB then this logic will fail becasue upper most bit
will go out of add0 register.

Fixing this by changing address configuration logic for erase block.

addr0 = (page << 16) addr1 = (page >> 16) & 0xffff;

Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I4950bb611780257629491ffbb42c91fcfedebc58
This commit is contained in:
Md Sadre Alam 2020-09-30 14:17:08 +05:30
parent 26f0f2b652
commit 43b1d16567
1 changed files with 1 additions and 0 deletions
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drivers/mtd/nand/qpic_nand.c
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@ -3844,6 +3844,7 @@ nand_result_t qpic_nand_blk_erase(struct mtd_info *mtd, uint32_t page)
* to do it again here.
*/
cfg.addr0 = page << 16;
cfg.addr1 = (page >> 16) & 0xffff;
cfg.cmd = 0xA;
cfg.cmd |= (QPIC_SPI_WP_SET | QPIC_SPI_HOLD_SET |
QPIC_SPI_TRANSFER_MODE_X1);