Printing on console while executing multi core command causes a race
condition in serial driver and results in data abort. Disable serial
console briefly during secondary cpu bring up to overcome the race
condition and data abort exception.
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Change-Id: I6b3cda3bd828cbcaf8e766f243f8137ab496a805
When dump_to_flash is set, and if the cur_type value is
set to QCA_WDT_LOG_DUMP_TYPE_INVALID, while loop is
executed forever. So, handled the error cases properly.
Change-Id: Ic3fdc01897b4fe9a45023074e9397af3c84f3aaa
Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org>
This changes add 8033 phy support in MP02.1(Ap & Db) RDP
in tiny nor flash
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ib35faba4321c70fed007c923ff0f5e618fad0276
This change update uncompress load address for ART
uncompress action, previously it was load at sys address.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ifce14c3cfe7746203acfcffa91adb2861f2b03db
This features allow to execute task on core 1.
This features not enable in tiny u-boot
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I986e7e3af840fd627dc5b6675931b79ab24ecb33
This changes remove the phy_name from all mpXX dts and
handle by driver itself.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ia2d0379151db0c68a0b28f5062e83f80579d37c1
This changes removes NAPA support from tiny U-boot config
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I057064d63a3ac0788275a4572242cc251a445a98
This changes reduce boot delay because of delay in pci
initialization
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I15d4ed26a07dafe0c8dd7eb8a666b3c7a3d2cfb6
This changes skip crash dump if warm-reset is enable.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I4a6d66ee0dc574c5f708a3d9d2964dbec0bbedb7
This update fix the the data abort happening while collecting
crash dump in secure boot.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I59bfd0032d3d580345fab721f750e50c9367e2b9
This change will enable config for serial training.
This change also fix the the logic to get most appropriate phase
out of passed phase.
This change also add support to read serial training offset from
partition table. Also patching freqency value & phase value to kernel.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: Ibb4a5cd80f16605e8e91bdf6a0c6c484edff1735
This patch tune's usb ssphy into SSC
instead of fixed offset.Also It ensures
Phy autoload should be done within
30us to 100us after pipe reset.
Change-Id: I192da047861a02d0b70d5c5c2f03715af7213c21
Signed-off-by: Manikanta Mylavarapu <mmanikan@codeaurora.org>
Removed identical device-tree to reuse original dts.
Affected boards: AC02 and OAK03
OAK03 to reuse HK01 dts and AC02 to reuse AC01 dts
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Change-Id: I5a70514370f394b15e68d5819cf8d1b52da14f3f
This patch will tune ssuniphy to fixed
offset instead of SSC.
Signed-off-by: Manikanta Mylavarapu <mmanikan@codeaurora.org>
Change-Id: Ieca1e079275092ea49fcc1ffa9ba1dadadd2a93a
This patch will update usb3 configurtaion
based on ssphy availability.
Since usb3 ssphy shared with pcie phy,
certain configuration need to be done based
on ssphy availability.
Signed-off-by: Manikanta Mylavarapu <mmanikan@codeaurora.org>
Change-Id: I474a6ea269e7778738ca9464dae510bb58e8bcea
This changes fixup the mtdparts without support of
MTD framework,This code read the partition details from env
variable and patch to kernel dts.
Change-Id: I829808620c35b57973dc0ae015131bc5019c4844
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
This changes enable nor enviornemnt support if its no flash with
eMMC and NAND is disabled.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I1ff389ed388fb7f72543cc87e852c360a965db48
We had identical device-tree for different RDPs
though they are the same except for machid.
This change enables reuse of a single device-tree
across RDPs with same configurations.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Change-Id: If81b431e4a6afe54e427fe0a52de275fdd29df00
This change fixes setting dirty bit in CMD_RCGR and configure GMAC
to run on GPLL4 clock source.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I01bb0e3af2da93f0464d41a6bd571480b1a4e581
Update usb controller and phy
configuration for enumeration.
Signed-off-by: Manikanta Mylavarapu <mmanikan@codeaurora.org>
Change-Id: I9e20fe5bf4c7abe7547f383ab58bff9b8dad64e0
This Gephy is internal phy driver for ethernet
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ia4e744c0fbd990bdc94fe93263ac2ddbe4cecf61
This change will remove GCC_SDCC1_MISC register from
SDCC clock configuration code path. Since in ipq5018 this
register is not available. so removining this register.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I980fc0f0ce24cd0da5610300608a5dd223c33941
This changes remove double calculation of N and D values.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I1c8444b5f6dbbc06a2b676477599978d6a91a681
This change is to remove SBL and U-Boot reserved memory nodes
in crashdump disabled case.
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Change-Id: Iea9d7e483e2766ec6124c9ec833dd81c3c8e9046
This changes initialize clock and enable the block of
Gephy, Uniphy, GMAC0 & GMAC1 and also udpate Rx & Tx clock
based on speed.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ia2627e17f7029c2d0d1cbb9eff26afb27aa1c057
This changes avoid initialize the usb if not present in dts.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I8d5666f1cceedb47b121ce6aefae93aa8c64d130
This change will add support for serial training in
QPIC.
Due to different PNR and PCB delays, serial read data
can come with different delays to QPIC. At high frequency
operations Rx clock should be adjusted according to delays
so that Rx Data can be captured correctly. CLK_CNTR_INIT_VAL_VEC
in NAND_FLASH_SPI_CFG register is a 12-bit vector which is divided
in 4 parts of 3 bits each representing delay of 4 serial input data
lines. Bit [2:0] corresponds to qspi_miso[0], bit [5:3] corresponds
to qspi_miso[1], bit [8:6] corresponds to qspi_miso[2] and bit [11:9]
corresponds to qspi_miso[3]. Delay of each qspi_miso line can be set
from 0 to 7.
For serial training the following rule should be followd.
1) SW should write a page with any known pattern in flash at lower
frequency.
2) Set the CLK_CNTR_INIT_VAL_VEC for qspi_miso[0] line.
3) Read that page repetitively in high frequency mode until it
gets data accurately.
4) Repeat above steps for other qspi_miso lines.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: If622809efff55fb2abe60f409a590abd5313741b
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Update usb configuration based
on hardware requirement.
Signed-off-by: Manikanta Mylavarapu <mmanikan@codeaurora.org>
Change-Id: I307834cddab8b3b060d78a98ed047725d265ee00
