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ipq5018: Add support S17C switch support

Browse source 
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ia3877ba97bc9cbe3b853c6f72ce6e5970395b43f
This commit is contained in:
Vandhiadevan Karunamoorthy 2020-05-24 15:50:56 +05:30 • committed by Prasanna Kumar Thoorvas Samyrao Muralidharan
parent cd1b381f34
commit d42f5e0c52
11 changed files with 319 additions and 103 deletions
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15
arch/arm/dts/ipq5018-db-mp03.1-c2.dts
View file

@ -70,4 +70,19 @@
nand: nand-controller@79B0000 {
status = "disabled";
};
gmac_cfg {
gmac_count = <1>;
ext_mdio_gpio = <36 37>;
gmac2_cfg {
unit = <1>;
base = <0x39D00000>;
phy_name = "IPQ MDIO1";
mac_pwr = <0xaa545>;
s17c_switch_enable = <1>;
switch_port_count = <4>;
switch_phy_address = <0 1 2 3>;
switch_gpio = <39>;
};
};
};

21
arch/arm/dts/ipq5018-mp03.1.dts
View file

@ -123,24 +123,19 @@
};
};
};
gmac_cfg {
gmac_count = <2>;
gmac1_cfg {
unit = <0>;
base = <0x39C00000>;
phy_address = <7>;
phy_name = "IPQ MDIO0";
};
gmac_cfg {
gmac_count = <1>;
ext_mdio_gpio = <36 37>;
gmac2_cfg {
unit = <1>;
base = <0x39D00000>;
phy_address = <1>;
phy_name = "IPQ MDIO1";
mac_pwr = <0xaa545>;
s17c_switch_enable = <1>;
switch_port_count = <4>;
switch_phy_address = <0 1 2 3>;
switch_gpio = <39>;
};
};
gmac_gpio{};
};

5
arch/arm/include/asm/arch-ipq5018/athrs17_phy.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2016 The Linux Foundation. All rights reserved.
* Copyright (c) 2015-2016, 2020 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -286,6 +286,9 @@
#define S17_MIB_PORT5 0x1500
#define S17_MIB_PORT6 0x1600
#define S17_MIB_COUNTER_ENABLE (1 << 0)
#define S17_MIB_NON_CLEAR (1 << 20)
#define S17_MIB_RXBROAD 0x0
#define S17_MIB_RXPAUSE 0x4
#define S17_MIB_RXMULTI 0x8

3
arch/arm/include/asm/arch-ipq5018/ipq5018_gmac.h
View file

@ -18,6 +18,7 @@
#include <configs/ipq5018.h>
#define GEPHY 0x7 /* Dummy */
#define S17C 0x1302
#define GEPHY_PHY_TYPE 0x1
#define NAPA_PHY_TYPE 0x2
@ -39,7 +40,6 @@
/* Poll demand definitions */
#define POLL_DATA (0x0)
/* Descriptior related definitions */
#define MAC_MAX_FRAME_SZ (1600)
@ -173,6 +173,7 @@
#define MII_PORT_SELECT (1 << 15)
#define GMII_PORT_SELECT (0 << 15)
#define FRAME_BURST_ENABLE (1 << 21)
#define JABBER_DISABLE (1 << 22)
#define JUMBO_FRAME_ENABLE (1 << 20)
#define HALF_DUPLEX_ENABLE (0 << 11)
#define FULL_DUPLEX_ENABLE (1 << 11)

179
board/qca/arm/ipq5018/ipq5018.c
View file

@ -310,7 +310,6 @@ int board_mmc_init(bd_t *bis)
int node, gpio_node;
int ret = 0;
qca_smem_flash_info_t *sfi = &qca_smem_flash_info;
node = fdt_path_offset(gd->fdt_blob, "mmc");
if (node < 0) {
printf("sdhci: Node Not found, skipping initialization\n");
@ -568,7 +567,6 @@ void board_nand_init(void)
* initializing
*/
int node;
node = fdt_path_offset(gd->fdt_blob, "/nand-controller");
if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) {
printf("QPIC: disabled, skipping initialization\n");
@ -614,12 +612,27 @@ unsigned long timer_read_counter(void)
return 0;
}
static void set_ext_mdio_gpio(void)
static void set_ext_mdio_gpio(int node)
{
/* mdc */
writel(0x7, (unsigned int *)GPIO_CONFIG_ADDR(36));
/* mdio */
writel(0x7, (unsigned int *)GPIO_CONFIG_ADDR(37));
unsigned int mdio_gpio[2] = {0};
int status = -1;
unsigned int *s17C_gpio_base;
status = fdtdec_get_int_array(gd->fdt_blob,
node,
"ext_mdio_gpio",
mdio_gpio,
2);
if (status >= 0) {
/* mdc */
s17C_gpio_base =
(unsigned int *)GPIO_CONFIG_ADDR(mdio_gpio[0]);
writel(0x7, s17C_gpio_base);
/* mdio */
s17C_gpio_base =
(unsigned int *)GPIO_CONFIG_ADDR(mdio_gpio[1]);
writel(0x7, s17C_gpio_base);
}
}
static void set_napa_phy_gpio(int gpio)
@ -628,42 +641,58 @@ static void set_napa_phy_gpio(int gpio)
napa_gpio_base = (unsigned int *)GPIO_CONFIG_ADDR(gpio);
writel(0x203, napa_gpio_base);
gpio_direction_output(gpio, 0x0);
writel(0x0, GPIO_IN_OUT_ADDR(gpio));
mdelay(500);
gpio_set_value(gpio, 0x1);
writel(0x1, GPIO_IN_OUT_ADDR(gpio));
}
static void reset_s17c_switch_gpio(int gpio)
{
unsigned int *switch_gpio_base =
(unsigned int *)GPIO_CONFIG_ADDR(gpio);
writel(0x203, switch_gpio_base);
writel(0x0, GPIO_IN_OUT_ADDR(gpio));
mdelay(500);
writel(0x2, GPIO_IN_OUT_ADDR(gpio));
}
static void cmn_blk_clk_set(void)
{
/* GMN block */
writel(0x1, GCC_CMN_BLK_AHB_CBCR);
mdelay(200);
mdelay(20);
writel(0x1, GCC_CMN_BLK_SYS_CBCR);
mdelay(200);
mdelay(20);
}
static void uniphy_clk_set(void)
{
writel(0x1, GCC_UNIPHY_AHB_CBCR);
mdelay(200);
mdelay(20);
writel(0x1, GCC_UNIPHY_SYS_CBCR);
mdelay(200);
mdelay(20);
writel(0x1, GCC_UNIPHY_RX_CBCR);
mdelay(20);
writel(0x1, GCC_UNIPHY_TX_CBCR);
mdelay(20);
}
static void gephy_port_clock_reset(void)
{
writel(0, GCC_GEPHY_RX_CBCR);
mdelay(200);
mdelay(20);
writel(0, GCC_GEPHY_TX_CBCR);
mdelay(200);
mdelay(20);
}
static void gmac0_clock_reset(void)
{
writel(0, GCC_GMAC0_RX_CBCR);
mdelay(200);
mdelay(20);
writel(0, GCC_GMAC0_TX_CBCR);
mdelay(200);
mdelay(20);
}
static void gmac_clk_src_init(void)
@ -699,13 +728,13 @@ static void gephy_reset(void)
reg_val = readl(GCC_GEPHY_BCR);
writel(reg_val | (GCC_GEPHY_BCR_BLK_ARES),
GCC_GEPHY_BCR);
mdelay(200);
mdelay(20);
writel(reg_val & (~GCC_GEPHY_BCR_BLK_ARES),
GCC_GEPHY_BCR);
reg_val = readl(GCC_GEPHY_MISC);
writel(reg_val | (GCC_GEPHY_MISC_ARES),
GCC_GEPHY_MISC);
mdelay(200);
mdelay(20);
writel(reg_val & (~GCC_GEPHY_MISC_ARES),
GCC_GEPHY_MISC);
}
@ -717,7 +746,7 @@ static void uniphy_reset(void)
reg_val = readl(GCC_UNIPHY_BCR);
writel(reg_val | (GCC_UNIPHY_BCR_BLK_ARES),
GCC_UNIPHY_BCR);
mdelay(200);
mdelay(20);
writel(reg_val & (~GCC_UNIPHY_BCR_BLK_ARES),
GCC_UNIPHY_BCR);
}
@ -729,7 +758,7 @@ static void gmac_reset(void)
reg_val = readl(GCC_GMAC0_BCR);
writel(reg_val | (GCC_GMAC0_BCR_BLK_ARES),
GCC_GMAC0_BCR);
mdelay(200);
mdelay(20);
writel(reg_val & (~GCC_GMAC0_BCR_BLK_ARES),
GCC_GMAC0_BCR);
@ -742,6 +771,69 @@ static void gmac_reset(void)
}
static void cmn_clock_init (void)
{
u32 reg_val = 0;
reg_val = readl(CMN_BLK_ADDR + 4);
reg_val = (reg_val & FREQUENCY_MASK) | INTERNAL_48MHZ_CLOCK;
writel(reg_val, CMN_BLK_ADDR + 0x4);
reg_val = readl(CMN_BLK_ADDR);
reg_val = reg_val | 0x40;
writel(reg_val, CMN_BLK_ADDR);
mdelay(1);
reg_val = reg_val & (~0x40);
writel(reg_val, CMN_BLK_ADDR);
mdelay(1);
writel(0xbf, CMN_BLK_ADDR);
mdelay(1);
writel(0xff, CMN_BLK_ADDR);
mdelay(1);
}
static void cmnblk_enable(void)
{
u32 reg_val;
reg_val = readl(TCSR_ETH_LDO_RDY_REG);
reg_val |= ETH_LDO_RDY;
writel(reg_val, TCSR_ETH_LDO_RDY_REG);
}
static void cmnblk_check_state(void)
{
u32 reg_val, times = 20;
while(times--)
{
reg_val = readl(CMN_PLL_PLL_LOCKED_REG);
if(reg_val & CMN_PLL_LOCKED) {
printf("cmbblk is stable %x\n",
reg_val);
break;
}
mdelay(10);
}
if(!times) {
printf("200ms have been over %x\n",
readl(CMN_PLL_PLL_LOCKED_REG));
}
}
static void uniphy_refclk_set(void)
{
/*
* This function drive the uniphy ref clock
* DEC_REFCLKOUTPUTCONTROLREGISTERS
* Its is configured as 25 MHZ
*/
#define UNIPHY_REF_CLK_CTRL_REG 0x98074
u32 reg_val = readl(UNIPHY_REF_CLK_CTRL_REG);
reg_val |= 0x2;
writel(reg_val, UNIPHY_REF_CLK_CTRL_REG);
mdelay(500);
}
static void gmac_clock_enable(void)
{
cmn_blk_clk_set();
@ -749,9 +841,13 @@ static void gmac_clock_enable(void)
gephy_port_clock_reset();
gmac0_clock_reset();
gmac_clk_src_init();
cmn_clock_init();
cmnblk_enable();
cmnblk_check_state();
gephy_reset();
uniphy_reset();
gmac_reset();
uniphy_refclk_set();
/* GMAC0 AHB clock enable */
writel(0x1, GCC_SNOC_GMAC0_AHB_CBCR);
@ -783,10 +879,11 @@ static void gmac_clock_enable(void)
int board_eth_init(bd_t *bis)
{
int status;
int gmac_gpio_node = 0;
int gmac_cfg_node = 0, offset = 0;
int loop = 0;
int switch_gpio = 0;
int phy_name_len = 0;
unsigned int tmp_phy_array[8] = {0};
char *phy_name_ptr = NULL;
gmac_cfg_node = fdt_path_offset(gd->fdt_blob, "/gmac_cfg");
@ -796,10 +893,8 @@ int board_eth_init(bd_t *bis)
*/
gmac_clock_enable();
status = fdtdec_get_uint(gd->fdt_blob,offset, "ext_mdio_gpio", 0);
if (status){
set_ext_mdio_gpio();
}
set_ext_mdio_gpio(gmac_cfg_node);
for (offset = fdt_first_subnode(gd->fdt_blob, gmac_cfg_node);
offset > 0;
offset = fdt_next_subnode(gd->fdt_blob, offset) , loop++) {
@ -821,18 +916,32 @@ int board_eth_init(bd_t *bis)
if (gmac_cfg[loop].phy_napa_gpio){
set_napa_phy_gpio(gmac_cfg[loop].phy_napa_gpio);
}
switch_gpio = fdtdec_get_uint(gd->fdt_blob, offset, "switch_gpio", 0);
if (switch_gpio) {
reset_s17c_switch_gpio(switch_gpio);
}
gmac_cfg[loop].phy_type = fdtdec_get_uint(gd->fdt_blob,
offset, "phy_type", -1);
gmac_cfg[loop].mac_pwr0 = fdtdec_get_uint(gd->fdt_blob,
offset, "mac_pwr0", 0);
gmac_cfg[loop].mac_pwr1 = fdtdec_get_uint(gd->fdt_blob,
offset, "mac_pwr1", 0);
gmac_cfg[loop].mac_pwr = fdtdec_get_uint(gd->fdt_blob,
offset, "mac_pwr", 0);
gmac_cfg[loop].ipq_swith = fdtdec_get_uint(gd->fdt_blob,
offset, "s17c_switch_enable", 0);
if (gmac_cfg[loop].ipq_swith) {
gmac_cfg[loop].switch_port_count = fdtdec_get_uint(
gd->fdt_blob,
offset, "switch_port_count", 0);
fdtdec_get_int_array(gd->fdt_blob, offset, "switch_phy_address",
tmp_phy_array, gmac_cfg[loop].switch_port_count);
for(int inner_loop = 0; inner_loop < gmac_cfg[loop].switch_port_count;
inner_loop++){
gmac_cfg[loop].switch_port_phy_address[inner_loop] =
(char)tmp_phy_array[inner_loop];
}
}
phy_name_ptr = (char*)fdt_getprop(gd->fdt_blob, offset,
"phy_name", &phy_name_len);
@ -842,12 +951,6 @@ int board_eth_init(bd_t *bis)
}
gmac_cfg[loop].unit = -1;
ipq_gmac_common_init(gmac_cfg);
gmac_gpio_node = fdt_path_offset(gd->fdt_blob, "gmac_gpio");
if (gmac_gpio_node) {
qca_gpio_init(gmac_gpio_node);
}
status = ipq_gmac_init(gmac_cfg);
return status;

22
board/qca/arm/ipq5018/ipq5018.h
View file

@ -27,11 +27,24 @@
#define GCC_GMAC0_TX_SRC_SEL_GEPHY_TX 0x100
#define GCC_GMAC1_RX_SRC_SEL_UNIPHY_RX 0x100
#define GCC_GMAC1_TX_SRC_SEL_UNIPHY_TX 0x100
#define CMN_PLL_PLL_LOCKED_REG 0x9B064
#define CMN_PLL_PLL_LOCKED_SIZE 0x4
#define CMN_PLL_LOCKED 0x4
/*
* CMN BLK clock
*/
#define GCC_CMN_BLK_AHB_CBCR 0x01856308
#define GCC_CMN_BLK_SYS_CBCR 0x0185630C
#define CMN_BLK_ADDR 0x0009B780
#define CMN_BLK_SIZE 0x100
#define FREQUENCY_MASK 0xfffffdf0
#define INTERNAL_48MHZ_CLOCK 0x7
#define TCSR_ETH_LDO_RDY_REG 0x19475C4
#define TCSR_ETH_LDO_RDY_SIZE 0x4
#define ETH_LDO_RDY 0x1
/*
* GEPHY Block Register
*/
@ -50,6 +63,8 @@
#define GCC_UNIPHY_SYS_CBCR 0x0185610C
#define GCC_UNIPHY_BCR_BLK_ARES 0x1
#define GCC_UNIPHY_MISC_ARES 0x32
#define GCC_UNIPHY_RX_CBCR 0x01856110
#define GCC_UNIPHY_TX_CBCR 0x01856114
/* GMAC0 GCC clock */
#define GCC_GMAC0_RX_CMD_RCGR 0x01868020
@ -422,6 +437,8 @@
unsigned int __invoke_psci_fn_smc(unsigned int, unsigned int,
unsigned int, unsigned int);
#define S17C_MAX_PORT 4
typedef struct {
u32 base;
int unit;
@ -429,9 +446,10 @@ typedef struct {
int phy_interface_mode;
int phy_napa_gpio;
int phy_type;
u32 mac_pwr0;
u32 mac_pwr1;
u32 mac_pwr;
int ipq_swith;
int switch_port_count;
int switch_port_phy_address[S17C_MAX_PORT];
const char phy_name[MDIO_NAME_LEN];
} ipq_gmac_board_cfg_t;

65
drivers/net/ipq5018/athrs17_phy.c
View file

@ -171,8 +171,15 @@ int athrs17_init_switch(void)
do {
udelay(10);
data = athrs17_reg_read(S17_MASK_CTRL_REG);
i++;
if (i == 10){
printf("Failed to reset S17C \n");
return -1;
}
} while (data & S17_MASK_CTRL_SOFT_RET);
i = 0;
do {
udelay(10);
data = athrs17_reg_read(S17_GLOBAL_INT0_REG);
@ -191,14 +198,12 @@ int athrs17_init_switch(void)
*********************************************************************/
void athrs17_reg_init(ipq_gmac_board_cfg_t *gmac_cfg)
{
uint32_t data;
athrs17_reg_write(S17_MAC_PWR_REG, gmac_cfg->mac_pwr);
data = athrs17_reg_read(S17_MAC_PWR_REG) | gmac_cfg->mac_pwr0;
athrs17_reg_write(S17_MAC_PWR_REG, data);
athrs17_reg_write(S17_P0STATUS_REG, (S17_SPEED_1000M | S17_TXMAC_EN |
S17_RXMAC_EN | S17_TX_FLOW_EN |
S17_RX_FLOW_EN | S17_DUPLEX_FULL));
athrs17_reg_write(S17_P0STATUS_REG, (S17_SPEED_1000M |
S17_TXMAC_EN |
S17_RXMAC_EN |
S17_DUPLEX_FULL));
athrs17_reg_write(S17_GLOFW_CTRL1_REG, (S17_IGMP_JOIN_LEAVE_DPALL |
S17_BROAD_DPALL |
@ -206,10 +211,12 @@ void athrs17_reg_init(ipq_gmac_board_cfg_t *gmac_cfg)
S17_UNI_FLOOD_DPALL));
athrs17_reg_write(S17_P5PAD_MODE_REG, S17_MAC0_RGMII_RXCLK_DELAY);
athrs17_reg_write(S17_P0PAD_MODE_REG, (S17_MAC0_RGMII_EN | \
S17_MAC0_RGMII_TXCLK_DELAY | S17_MAC0_RGMII_RXCLK_DELAY | \
(0x1 << S17_MAC0_RGMII_TXCLK_SHIFT) | \
(0x3 << S17_MAC0_RGMII_RXCLK_SHIFT)));
athrs17_reg_write(S17_P0PAD_MODE_REG, (S17_MAC0_RGMII_EN |
S17_MAC0_RGMII_TXCLK_DELAY |
S17_MAC0_RGMII_RXCLK_DELAY |
(0x1 << S17_MAC0_RGMII_TXCLK_SHIFT) |
(0x2 << S17_MAC0_RGMII_RXCLK_SHIFT)));
printf("%s: complete\n", __func__);
}
@ -223,19 +230,16 @@ void athrs17_reg_init_lan(ipq_gmac_board_cfg_t *gmac_cfg)
{
uint32_t reg_val;
athrs17_reg_write(S17_P6STATUS_REG, (S17_SPEED_1000M | S17_TXMAC_EN |
S17_RXMAC_EN |
S17_DUPLEX_FULL));
reg_val = athrs17_reg_read(S17_MAC_PWR_REG) | gmac_cfg->mac_pwr1;
athrs17_reg_write(S17_MAC_PWR_REG, reg_val);
athrs17_reg_write(S17_P6STATUS_REG, (S17_SPEED_1000M |
S17_TXMAC_EN |
S17_RXMAC_EN |
S17_DUPLEX_FULL));
athrs17_reg_write(S17_MAC_PWR_REG, gmac_cfg->mac_pwr);
reg_val = athrs17_reg_read(S17_P6PAD_MODE_REG);
athrs17_reg_write(S17_P6PAD_MODE_REG, (reg_val | S17_MAC6_SGMII_EN));
reg_val = athrs17_reg_read(S17_PWS_REG);
athrs17_reg_write(S17_PWS_REG, (reg_val |
S17c_PWS_SERDES_ANEG_DISABLE));
athrs17_reg_write(S17_PWS_REG, 0x2613a0);
athrs17_reg_write(S17_SGMII_CTRL_REG,(S17c_SGMII_EN_PLL |
S17c_SGMII_EN_RX |
@ -252,6 +256,8 @@ void athrs17_reg_init_lan(ipq_gmac_board_cfg_t *gmac_cfg)
S17c_SGMII_PAUSE_25M |
S17c_SGMII_HALF_DUPLEX_25M |
S17c_SGMII_FULL_DUPLEX_25M));
athrs17_reg_write(S17_MODULE_EN_REG, S17_MIB_COUNTER_ENABLE);
}
struct athrs17_regmap {
@ -260,13 +266,18 @@ struct athrs17_regmap {
};
struct athrs17_regmap regmap[] = {
{ 0x000, 0x0e0 },
{ 0x100, 0x168 },
{ 0x200, 0x270 },
{ 0x400, 0x454 },
{ 0x600, 0x718 },
{ 0x800, 0xb70 },
{ 0xC00, 0xC80 },
{ 0x000, 0x0e4 },
{ 0x100, 0x168 },
{ 0x200, 0x270 },
{ 0x400, 0x454 },
{ 0x600, 0x718 },
{ 0x800, 0xb70 },
{ 0xC00, 0xC80 },
{ 0x1100, 0x11a7 },
{ 0x1200, 0x12a7 },
{ 0x1300, 0x13a7 },
{ 0x1400, 0x14a7 },
{ 0x1600, 0x16a7 },
};
int do_ar8xxx_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {

87
drivers/net/ipq5018/ipq5018_gmac.c
View file

@ -37,6 +37,7 @@ uchar ipq_def_enetaddr[6] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55};
phy_info_t *phy_info[IPQ5018_PHY_MAX] = {0};
extern int ipq_mdio_read(int mii_id, int regnum, ushort *data);
extern int ipq_mdio_write(int mii_id, int regnum, u16 value);
extern int ipq5018_mdio_read(int mii_id, int regnum, ushort *data);
extern int ipq_qca8033_phy_init(struct phy_ops **ops, u32 phy_id);
extern int ipq_qca8081_phy_init(struct phy_ops **ops, u32 phy_id);
@ -83,15 +84,18 @@ static void ipq_eth_mac_cfg(struct eth_device *dev)
struct eth_mac_regs *mac_reg = (struct eth_mac_regs *)priv->mac_regs_p;
uint ipq_mac_cfg = 0;
uint ipq_mac_framefilter = 0;
ipq_mac_framefilter = PROMISCUOUS_MODE_ON;
ipq_mac_cfg |= (FRAME_BURST_ENABLE | JUMBO_FRAME_ENABLE |
ipq_mac_cfg |= (FRAME_BURST_ENABLE | JUMBO_FRAME_ENABLE | JABBER_DISABLE |
TX_ENABLE | RX_ENABLE | FULL_DUPLEX_ENABLE);
writel(ipq_mac_cfg, &mac_reg->conf);
writel(ipq_mac_framefilter, &mac_reg->framefilt);
}
static void ipq_eth_dma_cfg(struct eth_device *dev)
@ -240,6 +244,7 @@ static inline u32 ipq_gmac_is_desc_empty(ipq_gmac_desc_t *fr)
{
return ((fr->length & DescSize1Mask) == 0);
}
static void ipq5018_gmac0_speed_clock_set(int speed_clock1,
int speed_clock2, int gmacid)
{
@ -280,7 +285,7 @@ static void ipq5018_gmac0_speed_clock_set(int speed_clock1,
static int ipq5018_phy_link_update(struct eth_device *dev)
{
struct ipq_eth_dev *priv = dev->priv;
u8 status;
u8 status = 1;
struct phy_ops *phy_get_ops;
fal_port_speed_t speed;
fal_port_duplex_t duplex;
@ -300,8 +305,9 @@ static int ipq5018_phy_link_update(struct eth_device *dev)
}
if (priv->ipq_swith) {
speed_clock1 = 0x1;
speed_clock1 = 0x101;
speed_clock2 = 0;
status = 0;
} else {
status = phy_get_ops->phy_get_link_status(priv->mac_unit,
priv->phy_address);
@ -315,28 +321,32 @@ static int ipq5018_phy_link_update(struct eth_device *dev)
speed_clock1 = 0x9;
speed_clock2 = 0x9;
printf ("eth%d %s Speed :%d %s duplex\n",
priv->mac_unit, lstatus[status], speed,
priv->mac_unit,
lstatus[status], speed,
dp[duplex]);
break;
case FAL_SPEED_100:
speed_clock1 = 0x9;
speed_clock2 = 0;
printf ("eth%d %s Speed :%d %s duplex\n",
priv->mac_unit, lstatus[status], speed,
priv->mac_unit,
lstatus[status], speed,
dp[duplex]);
break;
case FAL_SPEED_1000:
speed_clock1 = 0x1;
speed_clock1 = 0x101;
speed_clock2 = 0;
printf ("eth%d %s Speed :%d %s duplex\n",
priv->mac_unit, lstatus[status], speed,
priv->mac_unit,
lstatus[status], speed,
dp[duplex]);
break;
case FAL_SPEED_2500:
speed_clock1 = 0x1;
speed_clock1 = 0x101;
speed_clock2 = 0;
printf ("eth%d %s Speed :%d %s duplex\n",
priv->mac_unit, lstatus[status], speed,
priv->mac_unit,
lstatus[status], speed,
dp[duplex]);
break;
default:
@ -346,7 +356,8 @@ static int ipq5018_phy_link_update(struct eth_device *dev)
}
if (priv->mac_unit){
if (priv->phy_type == QCA8081_PHY_TYPE)
if (priv->phy_type == QCA8081_PHY_TYPE ||
priv->phy_type == QCA8081_1_1_PHY)
ppe_uniphy_mode_set(PORT_WRAPPER_SGMII_PLUS);
else
ppe_uniphy_mode_set(PORT_WRAPPER_SGMII_FIBER);
@ -368,7 +379,9 @@ int ipq_eth_init(struct eth_device *dev, bd_t *this)
struct eth_dma_regs *dma_reg = (struct eth_dma_regs *)priv->dma_regs_p;
u32 data;
if(ipq5018_phy_link_update(dev) < 0);
if(ipq5018_phy_link_update(dev) < 0) {
return -1;
}
priv->next_rx = 0;
priv->next_tx = 0;
@ -597,8 +610,49 @@ int ipq_gmac_init(ipq_gmac_board_cfg_t *gmac_cfg)
if (ret)
goto init_failed;
if (ipq_gmac_macs[i]->ipq_swith){
if (ipq_athrs17_init(gmac_cfg) != 0)
printf(" S17C switch init failed \n");
/* S17C switch Id */
phy_chip_id = S17C;
for (int port = 0;
port < gmac_cfg->switch_port_count;
++port) {
u32 phy_val;
/* phy powerdown */
ipq_mdio_write(port, 0x0, 0x0800);
phy_val = ipq_mdio_read(port, 0x3d, NULL);
phy_val &= ~0x0040;
ipq_mdio_write(port, 0x3d, phy_val);
/*
* PHY will stop the tx clock for a while when link is down
* en_anychange debug port 0xb bit13 = 0 //speed up link down tx_clk
* sel_rst_80us debug port 0xb bit10 = 0 //speed up speed mode change to 2'b10 tx_clk
*/
phy_val = ipq_mdio_read(port, 0xb, NULL);
phy_val &= ~0x2400;
ipq_mdio_write(port, 0xb, phy_val);
mdelay(100);
}
if (ipq_athrs17_init(gmac_cfg) != 0){
printf("S17C switch init failed port \n");
}
for (int port = 0;
port < gmac_cfg->switch_port_count;
++port) {
u32 value;
ipq_mdio_write(port, MII_ADVERTISE, ADVERTISE_ALL |
ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
/*
* phy reg 0x9, b10,1 = Prefer multi-port device (master)
*/
ipq_mdio_write(port, MII_CTRL1000, (0x0400|ADVERTISE_1000FULL));
ipq_mdio_write(port, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
value = ipq_mdio_read(port, 0, NULL);
value &= (~(1<<12));
ipq_mdio_write(port, 0, value);
mdelay(100);
}
} else {
phy_chip_id1 = ipq_mdio_read(
ipq_gmac_macs[i]->phy_address,
@ -645,6 +699,8 @@ int ipq_gmac_init(ipq_gmac_board_cfg_t *gmac_cfg)
&ipq_gmac_macs[i]->ops,
ipq_gmac_macs[i]->phy_address);
break;
case S17C:
break;
default:
printf("GMAC%d : Invalid PHY ID \n", i);
break;
@ -672,8 +728,3 @@ init_failed:
return -ENOMEM;
}
void ipq_gmac_common_init(ipq_gmac_board_cfg_t *gmac_cfg)
{
return;
}

20
drivers/net/ipq5018/ipq5018_uniphy.c
View file

@ -64,15 +64,19 @@ static void ppe_uniphy_sgmii_mode_set(uint32_t mode)
writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE +
UNIPHY_PLL_RESET_REG_OFFSET);
mdelay(500);
mdelay(10);
writel(UNIPHY_PLL_RESET_REG_DEFAULT_VALUE, PPE_UNIPHY_BASE +
UNIPHY_PLL_RESET_REG_OFFSET);
mdelay(500);
mdelay(10);
writel(0x0, GCC_UNIPHY_RX_CBCR);
udelay(500);
writel(0x0, GCC_UNIPHY_TX_CBCR);
udelay(500);
writel(0x0, GCC_GMAC1_RX_CBCR);
udelay(500);
writel(0x0, GCC_GMAC1_TX_CBCR);
udelay(500);
switch (mode) {
case PORT_WRAPPER_SGMII_FIBER:
@ -99,11 +103,23 @@ static void ppe_uniphy_sgmii_mode_set(uint32_t mode)
ppe_gcc_uniphy_soft_reset();
writel(0x1, GCC_UNIPHY_RX_CBCR);
udelay(500);
writel(0x1, GCC_UNIPHY_TX_CBCR);
udelay(500);
writel(0x1, GCC_GMAC1_RX_CBCR);
udelay(500);
writel(0x1, GCC_GMAC1_TX_CBCR);
udelay(500);
ppe_uniphy_calibration();
/*
* Force Speed mode enable
*/
writel((readl(PPE_UNIPHY_BASE + UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4) |
UNIPHY_FORCE_SPEED_25M),
PPE_UNIPHY_BASE + UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4);
}
void ppe_uniphy_mode_set(uint32_t mode)

3
drivers/net/ipq5018/ipq5018_uniphy.h
View file

@ -43,6 +43,9 @@
#define UNIPHY_CH1_CH0_SGMII (1 << 1)
#define UNIPHY_CH0_ATHR_CSCO_MODE_25M (1 << 0)
#define UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4 0x480
#define UNIPHY_FORCE_SPEED_25M (1 << 3)
#define UNIPHY_INSTANCE_LINK_DETECT 0x570
#define UNIPHY_MISC2_REG_OFFSET 0x218

2
include/configs/ipq5018.h
View file

@ -304,7 +304,7 @@ extern loff_t board_env_size;
#define CONFIG_BOOTARGS "console=ttyMSM0,115200n8"
#define QCA_ROOT_FS_PART_NAME "rootfs"
#define CONFIG_BOOTDELAY 2
#define CONFIG_BOOTDELAY 5
#define NUM_ALT_PARTITION 16