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ipq5018: Fix GMAC clock source command register.

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This change fixes setting dirty bit in CMD_RCGR and configure GMAC
to run on GPLL4 clock source.

Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I01bb0e3af2da93f0464d41a6bd571480b1a4e581
This commit is contained in:
Vandhiadevan Karunamoorthy 2020-06-03 09:36:14 +05:30 • committed by Prasanna Kumar Thoorvas Samyrao Muralidharan
parent e85ae5f50d
commit 701787232f
2 changed files with 19 additions and 1 deletions
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19
board/qca/arm/ipq5018/ipq5018.c
View file

@ -733,7 +733,7 @@ static void gmac_clock_disable(void)
static void gmac_clk_src_init(void)
{
u32 reg_val;
u32 reg_val, iGmac_id, iTxRx;
/*select source of GMAC*/
reg_val = readl(GCC_GMAC0_RX_CFG_RCGR);
@ -756,9 +756,26 @@ static void gmac_clk_src_init(void)
reg_val |= GCC_GMAC1_TX_SRC_SEL_UNIPHY_TX;
writel(reg_val, GCC_GMAC1_TX_CFG_RCGR);
/* update above clock configuration */
for (iGmac_id = 0; iGmac_id < 2; ++iGmac_id) {
for (iTxRx = 0; iTxRx < 2; ++iTxRx){
reg_val = 0;
reg_val = readl(GCC_GMAC0_RX_CMD_RCGR +
(iTxRx * 8) + (iGmac_id * 0x10));
reg_val &= ~0x1;
reg_val |= 0x1;
writel(reg_val, GCC_GMAC0_RX_CMD_RCGR +
(iTxRx * 8) + (iGmac_id * 0x10));
}
}
reg_val = readl(GCC_GMAC_CFG_RCGR);
reg_val = 0x209;
writel(reg_val, GCC_GMAC_CFG_RCGR);
reg_val = readl(GCC_GMAC_CMD_RCGR);
reg_val &= ~0x1;
reg_val |= 0x1;
writel(reg_val, GCC_GMAC_CMD_RCGR);
}
static void gephy_reset(void)

1
board/qca/arm/ipq5018/ipq5018.h
View file

@ -24,6 +24,7 @@
#define GCC_MDIO0_BASE 0x1858000
#define GCC_GMAC_CFG_RCGR 0x01868084
#define GCC_GMAC_CMD_RCGR 0x01868080
#define GCC_GMAC_BASE 0x01868000