mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
Merge "ipq5018: Fix usb configuration"
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commit
f637a16ef2
2 changed files with 103 additions and 133 deletions
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@ -775,21 +775,23 @@ void board_usb_deinit(int id)
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return;
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/* Enable USB PHY Power down */
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setbits_le32(USB30_PHY_1_QUSB2PHY_BASE + 0xB4, 0x1);
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setbits_le32(QUSB2PHY_BASE + 0xA4, 0x0);
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/* Disable clocks */
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writel(0x8000, GCC_USB0_PHY_CFG_AHB_CBCR);
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writel(0x8ff0, GCC_USB0_MASTER_CBCR);
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writel(0, GCC_SYS_NOC_USB0_AXI_CBCR);
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writel(0, GCC_SNOC_BUS_TIMEOUT2_AHB_CBCR);
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writel(0, GCC_USB0_SLEEP_CBCR);
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writel(0, GCC_USB0_MOCK_UTMI_CBCR);
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writel(0, GCC_USB0_AUX_CBCR);
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writel(0x0, GCC_USB0_PHY_CFG_AHB_CBCR);
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writel(0x4220, GCC_USB0_MASTER_CBCR);
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writel(0x0, GCC_SYS_NOC_USB0_AXI_CBCR);
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writel(0x0, GCC_USB0_SLEEP_CBCR);
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writel(0x0, GCC_USB0_MOCK_UTMI_CBCR);
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writel(0x0, GCC_USB0_AUX_CBCR);
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writel(0x0, GCC_USB0_LFPS_CBCR);
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/* GCC_QUSB2_0_PHY_BCR */
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set_mdelay_clearbits_le32(GCC_QUSB2_0_PHY_BCR, 0x1, 10);
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/* GCC_USB0_PHY_BCR */
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set_mdelay_clearbits_le32(GCC_USB0_PHY_BCR, 0x1, 10);
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/* GCC Reset USB BCR */
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set_mdelay_clearbits_le32(GCC_USB0_BCR, 0x1, 10);
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/* Deselect the usb phy mux */
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writel(0x0, TCSR_USB_PCIE_SEL);
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}
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static void usb_clock_init(int id)
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@ -808,13 +810,22 @@ static void usb_clock_init(int id)
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cfg = (GCC_USB_MOCK_UTMI_SRC_SEL |
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GCC_USB_MOCK_UTMI_SRC_DIV);
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writel(cfg, GCC_USB0_MOCK_UTMI_CFG_RCGR);
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writel(UTMI_M, GCC_USB0_MOCK_UTMI_M);
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writel(UTMI_N, GCC_USB0_MOCK_UTMI_N);
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writel(UTMI_D, GCC_USB0_MOCK_UTMI_D);
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writel(GCC_USB_MOCK_UTMI_CLK_DIV, GCC_USB0_MOCK_UTMI_CBCR);
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writel(CMD_UPDATE, GCC_USB0_MOCK_UTMI_CMD_RCGR);
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mdelay(100);
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writel(ROOT_EN, GCC_USB0_MOCK_UTMI_CMD_RCGR);
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/* Configure usb0_lfps_cmd_rcgr */
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cfg = (GCC_USB0_LFPS_CFG_SRC_SEL |
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GCC_USB0_LFPS_CFG_SRC_DIV);
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writel(cfg, GCC_USB0_LFPS_CFG_RCGR);
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writel(LFPS_M, GCC_USB0_LFPS_M);
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writel(LFPS_N, GCC_USB0_LFPS_N);
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writel(LFPS_D, GCC_USB0_LFPS_D);
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writel(CMD_UPDATE, GCC_USB0_LFPS_CMD_RCGR);
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mdelay(100);
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writel(ROOT_EN, GCC_USB0_LFPS_CMD_RCGR);
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/* Configure usb0_aux_clk_src */
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cfg = (GCC_USB0_AUX_CFG_SRC_SEL |
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GCC_USB0_AUX_CFG_SRC_DIV);
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@ -825,132 +836,61 @@ static void usb_clock_init(int id)
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/* Configure CBCRs */
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writel(CLK_DISABLE, GCC_SYS_NOC_USB0_AXI_CBCR);
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writel(CLK_DISABLE, GCC_SNOC_BUS_TIMEOUT2_AHB_CBCR);
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writel(CLK_ENABLE, GCC_SYS_NOC_USB0_AXI_CBCR);
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writel((readl(GCC_USB0_MASTER_CBCR) | CLK_ENABLE),
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GCC_USB0_MASTER_CBCR);
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writel(CLK_ENABLE, GCC_SNOC_BUS_TIMEOUT2_AHB_CBCR);
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writel(CLK_ENABLE, GCC_USB0_SLEEP_CBCR);
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writel(CLK_ENABLE, GCC_USB0_MOCK_UTMI_CBCR);
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writel((CLK_ENABLE | NOC_HANDSHAKE_FSM_EN),
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GCC_USB0_PHY_CFG_AHB_CBCR);
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writel(CLK_ENABLE, GCC_USB0_PHY_CFG_AHB_CBCR);
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writel(CLK_ENABLE, GCC_USB0_AUX_CBCR);
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writel(CLK_ENABLE, GCC_USB0_PIPE_CBCR);
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writel(CLK_ENABLE, GCC_USB0_LFPS_CBCR);
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}
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static void usb_init_hsphy(void __iomem *phybase)
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{
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/* Enable QUSB2PHY Power down */
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setbits_le32(phybase+0xB4, 0x1);
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/* PHY Config Sequence */
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/* QUSB2PHY_PLL:PLL Feedback Divider Value */
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out_8(phybase+0x00, 0x14);
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/* QUSB2PHY_PORT_TUNE1: USB Product Application Tuning Register A */
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out_8(phybase+0x80, 0xF8);
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/* QUSB2PHY_PORT_TUNE2: USB Product Application Tuning Register B */
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out_8(phybase+0x84, 0xB3);
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/* QUSB2PHY_PORT_TUNE3: USB Product Application Tuning Register C */
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out_8(phybase+0x88, 0x83);
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/* QUSB2PHY_PORT_TUNE4: USB Product Application Tuning Register D */
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out_8(phybase+0x8C, 0xC0);
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/* QUSB2PHY_PORT_TEST2 */
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out_8(phybase+0x9C, 0x14);
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/* QUSB2PHY_PLL_TUNE: PLL Test Configuration */
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out_8(phybase+0x08, 0x30);
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/* QUSB2PHY_PLL_USER_CTL1: PLL Control Configuration */
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out_8(phybase+0x0C, 0x79);
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/* QUSB2PHY_PLL_USER_CTL2: PLL Control Configuration */
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out_8(phybase+0x10, 0x21);
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/* QUSB2PHY_PORT_TUNE5 */
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out_8(phybase+0x90, 0x00);
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/* QUSB2PHY_PLL_PWR_CTL: PLL Manual SW Programming
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* and Biasing Power Options */
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out_8(phybase+0x18, 0x00);
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/* QUSB2PHY_PLL_AUTOPGM_CTL1: Auto vs. Manual PLL/Power-mode
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* programming State Machine Control Options */
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out_8(phybase+0x1C, 0x9F);
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/* QUSB2PHY_PLL_TEST: PLL Test Configuration-Disable diff ended clock */
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out_8(phybase+0x04, 0x80);
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/* Disable QUSB2PHY Power down */
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clrbits_le32(phybase+0xB4, 0x1);
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/* Disable USB PHY Power down */
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setbits_le32(phybase + 0xA4, 0x1);
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/* Enable override ctrl */
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writel(UTMI_PHY_OVERRIDE_EN, phybase + USB_PHY_CFG0);
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/* Enable POR*/
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writel(POR_EN, phybase + USB_PHY_UTMI_CTRL5);
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udelay(15);
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/* Configure frequency select value*/
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writel(FREQ_SEL, phybase + USB_PHY_FSEL_SEL);
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/* Configure refclk frequency */
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writel(COMMONONN | FSEL | RETENABLEN,
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phybase + USB_PHY_HS_PHY_CTRL_COMMON0);
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/* select refclk source */
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writel(CLKCORE, phybase + USB_PHY_REFCLK_CTRL);
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/* select ATERESET*/
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writel(POR_EN & ATERESET, phybase + USB_PHY_UTMI_CTRL5);
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writel(USB2_SUSPEND_N_SEL | USB2_SUSPEND_N | USB2_UTMI_CLK_EN,
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phybase + USB_PHY_HS_PHY_CTRL2);
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writel(0x0, phybase + USB_PHY_UTMI_CTRL5);
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writel(USB2_SUSPEND_N | USB2_UTMI_CLK_EN,
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phybase + USB_PHY_HS_PHY_CTRL2);
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/* Disable override ctrl */
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writel(0x0, phybase + USB_PHY_CFG0);
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}
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static void usb_init_ssphy(void __iomem *phybase)
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{
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out_8(phybase + USB3_PHY_POWER_DOWN_CONTROL,0x1);
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out_8(phybase + QSERDES_COM_SYSCLK_EN_SEL,0x1a);
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out_8(phybase + QSERDES_COM_BIAS_EN_CLKBUFLR_EN,0x08);
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out_8(phybase + QSERDES_COM_CLK_SELECT,0x30);
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out_8(phybase + QSERDES_COM_BG_TRIM,0x0f);
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out_8(phybase + QSERDES_RX_UCDR_FASTLOCK_FO_GAIN,0x0b);
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out_8(phybase + QSERDES_COM_SVS_MODE_CLK_SEL,0x01);
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out_8(phybase + QSERDES_COM_HSCLK_SEL,0x00);
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out_8(phybase + QSERDES_COM_CMN_CONFIG,0x06);
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out_8(phybase + QSERDES_COM_PLL_IVCO,0x0f);
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out_8(phybase + QSERDES_COM_SYS_CLK_CTRL,0x06);
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out_8(phybase + QSERDES_COM_DEC_START_MODE0,0x68);
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out_8(phybase + QSERDES_COM_DIV_FRAC_START1_MODE0,0xAB);
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out_8(phybase + QSERDES_COM_DIV_FRAC_START2_MODE0,0xAA);
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out_8(phybase + QSERDES_COM_DIV_FRAC_START3_MODE0,0x02);
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out_8(phybase + QSERDES_COM_CP_CTRL_MODE0,0x09);
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out_8(phybase + QSERDES_COM_PLL_RCTRL_MODE0,0x16);
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out_8(phybase + QSERDES_COM_PLL_CCTRL_MODE0,0x28);
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out_8(phybase + QSERDES_COM_INTEGLOOP_GAIN0_MODE0,0xA0);
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out_8(phybase + QSERDES_COM_LOCK_CMP1_MODE0,0xAA);
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out_8(phybase + QSERDES_COM_LOCK_CMP2_MODE0,0x29);
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out_8(phybase + QSERDES_COM_LOCK_CMP3_MODE0,0x00);
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out_8(phybase + QSERDES_COM_CORE_CLK_EN,0x00);
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out_8(phybase + QSERDES_COM_LOCK_CMP_CFG,0x00);
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out_8(phybase + QSERDES_COM_VCO_TUNE_MAP,0x00);
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out_8(phybase + QSERDES_COM_BG_TIMER,0x0a);
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out_8(phybase + QSERDES_COM_SSC_EN_CENTER,0x01);
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out_8(phybase + QSERDES_COM_SSC_PER1,0x7D);
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out_8(phybase + QSERDES_COM_SSC_PER2,0x01);
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out_8(phybase + QSERDES_COM_SSC_ADJ_PER1,0x00);
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out_8(phybase + QSERDES_COM_SSC_ADJ_PER2,0x00);
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out_8(phybase + QSERDES_COM_SSC_STEP_SIZE1,0x0A);
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out_8(phybase + QSERDES_COM_SSC_STEP_SIZE2,0x05);
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out_8(phybase + QSERDES_RX_UCDR_SO_GAIN,0x06);
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out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2,0x02);
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out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3,0x6c);
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out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3,0x4c);
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out_8(phybase + QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4,0xb8);
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out_8(phybase + QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL,0x77);
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out_8(phybase + QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2,0x80);
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out_8(phybase + QSERDES_RX_SIGDET_CNTRL,0x03);
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out_8(phybase + QSERDES_RX_SIGDET_DEGLITCH_CNTRL,0x16);
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out_8(phybase + QSERDES_RX_SIGDET_ENABLES,0x0c);
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out_8(phybase + QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_D,0x45);
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out_8(phybase + QSERDES_TX_RCV_DETECT_LVL_2,0x12);
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out_8(phybase + QSERDES_TX_LANE_MODE,0x06);
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out_8(phybase + PCS_TXDEEMPH_M6DB_V0,0x15);
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out_8(phybase + PCS_TXDEEMPH_M3P5DB_V0,0x0e);
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out_8(phybase + PCS_FLL_CNTRL2,0x83);
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out_8(phybase + PCS_FLL_CNTRL1,0x02);
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out_8(phybase + PCS_FLL_CNT_VAL_L,0x09);
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out_8(phybase + PCS_FLL_CNT_VAL_H_TOL,0xa2);
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out_8(phybase + PCS_FLL_MAN_CODE,0x85);
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out_8(phybase + PCS_LOCK_DETECT_CONFIG1,0xd1);
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out_8(phybase + PCS_LOCK_DETECT_CONFIG2,0x1f);
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out_8(phybase + PCS_LOCK_DETECT_CONFIG3,0x47);
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out_8(phybase + PCS_POWER_STATE_CONFIG2,0x1b);
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out_8(phybase + PCS_RXEQTRAINING_WAIT_TIME,0x75);
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out_8(phybase + PCS_RXEQTRAINING_RUN_TIME,0x13);
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out_8(phybase + PCS_LFPS_TX_ECSTART_EQTLOCK,0x86);
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out_8(phybase + PCS_PWRUP_RESET_DLY_TIME_AUXCLK,0x04);
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out_8(phybase + PCS_TSYNC_RSYNC_TIME,0x44);
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out_8(phybase + PCS_RCVR_DTCT_DLY_P1U2_L,0xe7);
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out_8(phybase + PCS_RCVR_DTCT_DLY_P1U2_H,0x03);
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out_8(phybase + PCS_RCVR_DTCT_DLY_U3_L,0x40);
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out_8(phybase + PCS_RCVR_DTCT_DLY_U3_H,0x00);
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out_8(phybase + PCS_RX_SIGDET_LVL,0x88);
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out_8(phybase + USB3_PCS_TXDEEMPH_M6DB_V0,0x17);
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out_8(phybase + USB3_PCS_TXDEEMPH_M3P5DB_V0,0x0f);
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out_8(phybase + QSERDES_RX_SIGDET_ENABLES,0x0);
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out_8(phybase + USB3_PHY_START_CONTROL,0x03);
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out_8(phybase + USB3_PHY_SW_RESET,0x00);
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/* select usb phy mux */
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writel(0x1, TCSR_USB_PCIE_SEL);
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writel(CLK_ENABLE, GCC_USB0_PHY_CFG_AHB_CBCR);
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writel(CLK_ENABLE, GCC_USB0_PIPE_CBCR);
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writel(CLK_DISABLE, GCC_USB0_PIPE_CBCR);
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udelay(100);
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/*set frequency initial value*/
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writel(0x1cb9, phybase + SSCG_CTRL_REG_4);
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writel(0x023a, phybase + SSCG_CTRL_REG_5);
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/*set spectrum spread count*/
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writel(0x1360, phybase + SSCG_CTRL_REG_3);
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/*set fstep*/
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writel(0x1, phybase + SSCG_CTRL_REG_1);
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writel(0xeb, phybase + SSCG_CTRL_REG_2);
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return;
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}
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static void usb_init_phy(int index)
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@ -982,8 +922,8 @@ static void usb_init_phy(int index)
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clrbits_le32(qusb2_phy_bcr, 0x1);
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mdelay(10);
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usb_init_hsphy((u32 *)USB30_PHY_1_QUSB2PHY_BASE);
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usb_init_ssphy((u32 *)USB30_PHY_1_USB3PHY_AHB2PHY_BASE);
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usb_init_hsphy((u32 *)QUSB2PHY_BASE);
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usb_init_ssphy((u32 *)USB3PHY_APB_BASE);
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}
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int ipq_board_usb_init(void)
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@ -166,11 +166,17 @@
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#define GUCTL 0x700C12C
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#define FLADJ 0x700C630
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#define USB30_PHY_1_QUSB2PHY_BASE 0x79000
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#define QUSB2PHY_BASE 0x5b000
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#define GCC_USB0_LFPS_CFG_SRC_SEL (0x1 << 8)
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#define GCC_USB0_LFPS_CFG_SRC_DIV (0x1f << 0)
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#define LFPS_M 0x1
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#define LFPS_N 0xfe
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#define LFPS_D 0xfd
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#define GCC_USB0_AUX_CFG_MODE_DUAL_EDGE (2 << 12)
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#define GCC_USB0_AUX_CFG_SRC_SEL (0 << 8)
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#define GCC_USB0_AUX_CFG_SRC_DIV (0 << 0)
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#define GCC_USB0_AUX_CFG_SRC_DIV (0x17 << 0)
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#define AUX_M 0x0
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#define AUX_N 0x0
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@ -181,20 +187,18 @@
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#define GCC_USB0_MASTER_CFG_RCGR_SRC_SEL (1 << 8)
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#define GCC_USB0_MASTER_CFG_RCGR_SRC_DIV (0xb << 0)
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#define GCC_USB0_MASTER_CFG_RCGR_SRC_DIV (0x7 << 0)
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#define GCC_USB_MOCK_UTMI_SRC_SEL (0 << 8)
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#define GCC_USB_MOCK_UTMI_SRC_DIV (1 << 0)
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#define GCC_USB_MOCK_UTMI_SRC_SEL (1 << 8)
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#define GCC_USB_MOCK_UTMI_SRC_DIV (0x13 << 0)
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#define UTMI_M 0x1
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#define UTMI_N 0xf7
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#define UTMI_D 0xf6
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#define GCC_USB_MOCK_UTMI_CLK_DIV (0x1 << 16)
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#define GCC_SNOC_BUS_TIMEOUT2_AHB_CBCR 0x01847014
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#define GCC_QUSB2_1_PHY_BCR 0x1841040
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#define USB30_PHY_2_QUSB2PHY_BASE 0x59000
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#define USB30_PHY_1_USB3PHY_AHB2PHY_BASE 0x78000
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#define USB30_PHY_2_USB2PHY_AHB2PHY_BASE 0x58000
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#define USB3PHY_APB_BASE 0x5d000
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#define USB3_PHY_POWER_DOWN_CONTROL 0x804
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#define QSERDES_COM_SYSCLK_EN_SEL 0xac
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@ -355,6 +359,32 @@
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#define ARM_PSCI_TZ_FN_AFFINITY_INFO ARM_PSCI_TZ_FN(4)
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#define CLK_ENABLE 0x1
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#define SSCG_CTRL_REG_1 0x9c
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#define SSCG_CTRL_REG_2 0xa0
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#define SSCG_CTRL_REG_3 0xa4
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#define SSCG_CTRL_REG_4 0xa8
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#define SSCG_CTRL_REG_5 0xac
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#define SSCG_CTRL_REG_6 0xb0
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#define USB_PHY_CFG0 0x94
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#define USB_PHY_UTMI_CTRL5 0x50
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#define USB_PHY_FSEL_SEL 0xB8
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#define USB_PHY_HS_PHY_CTRL_COMMON0 0x54
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#define USB_PHY_REFCLK_CTRL 0xA0
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#define USB_PHY_HS_PHY_CTRL2 0x64
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#define USB_PHY_UTMI_CTRL0 0x3c
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#define UTMI_PHY_OVERRIDE_EN (1 << 1)
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#define POR_EN (1 << 1)
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#define FREQ_SEL (1 << 0)
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#define COMMONONN (1 << 7)
|
||||
#define FSEL (1 << 4)
|
||||
#define RETENABLEN (1 << 3)
|
||||
#define USB2_SUSPEND_N_SEL (1 << 3)
|
||||
#define USB2_SUSPEND_N (1 << 2)
|
||||
#define USB2_UTMI_CLK_EN (1 << 1)
|
||||
#define CLKCORE (1 << 1)
|
||||
#define ATERESET ~(1 << 0)
|
||||
|
||||
unsigned int __invoke_psci_fn_smc(unsigned int, unsigned int,
|
||||
unsigned int, unsigned int);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue