This change will enable page_scope_read & multipage_read support for
QPIC.
QPIC version 2.0 onwards , QPIC support page_scope_read &
multipage_read command to enhance the read performance.
In normal page read command SW is needed to write EXEC_CMD register
for each Code word and collect any Status related to that CW before
issueing EXEC_CMD for next CW.
For page_scope read command SW is required to issue EXEC_CMD
only once for a page. Controller HW takes care of Codeword specific
details and automatically returns status associated with each CW to
BAM pipe, dedicated for status deposition.
enabling all bits in NAND_AUTO_STATUS_EN will require 4 data
descriptors of 24 bytes each. This will publish all NANDc status
registers in system memory.
For multipage_read command SW is required to issue EXEC_CMD only
once for all the pages which configured in QPIC_NAND_MULTI_PAGE_CMD
register.
All interrupts will be operational and valid in these modes.
To check the status for each codeword, it is not possible to access
the status registers while the read command is operational in
page_scope & multi_page read modes. Hence, another feature to publish the
status data (for all NAND status registers) by programming the
NAND_AUTO_STATUS_EN register.
For serial NAND:
Read command for page_scope_read = 0x78800032 (QPIC_NAND_FLASH_CMD)
Read command for multi_page_read = 0x78400032 (QPIC_NAND_FLASH_CMD)
For Parallel NAND:
Read command for page_scope_read = 0x00800032 (QPIC_NAND_FLASH_CMD)
Read command for multi_page_read = 0x00400032 (QPIC_NAND_FLASH_CMD)
Now we fixed maximum data bytes read in one go 128KiB(2KiB page),
256KiB (4KiB page), 512 KiB (8kiB page), because from upper layer
we are getting more than 128KiB data bytes request in one go. if so
just changing the value of "MAX_MULTI_PAGE" macro will increase the
maximum data bytes in one go.
Change-Id: I48eea51ff8f5f79f3490d8a538c295ecc3eeee19
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Since nand configuration is fixed across all HK boards,
removing the nand gpio_entries from device tree and
adding static board param entries. This helps reduce
image footprint and opens up space for new board support.
Change-Id: I89bc11165a6cdfcdb3b4650a73cbeea17895f991
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Fidelix SPI NAND FM35X2GA has two planes namely plane 0 and plane 1.
This change adds the support to calculate the plane bit accordingly
and use the same for command formation.
Change-Id: I6fb4b652e1c897f248cb9ad8914f67be7a7365f3
Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
This change will add support for serial nand.
QPIC-2.1.1 supports parallel nand as well as serial nand.
QPIC will operate either in parallel configuration or
serial nand. Both can't work together.
This change will support initially four serial nand parts.
MT29F1G01ABBFDWB-IT (Micron-0x2C,0x15, 2K + 128)
GD5F1GQ4RE9IG (Giga Device-0xC8,0xC1, 2K + 128)
GD5F2GQ5REYIH (Giga Device-0xC8,0x22, 2K + 64)
GD5F1GQ4RE9IH (Giga Device-0xC8, 0xC9, 2K + 64)
Device Internal ECC is disabled for all three devices. This change will
enabele QPIC ECC engine.
For MT29F1G01ABBFDWB-IT 4-bit ECC as well 8-bit ECC will be supported.
For GD5F1GQ4RE9IG 4-bit ECC as well 8-bit ECC will be supported.
For GD5F2GQ5REYIH only 4-bit ECC will be supported due to 64-bytes spare.
For GD5F1GQ4RE9IH only 4-bit ECC will be supported due to 64-bytes spare.
Change-Id: I3f38f9c76b7bb235bb335a481fbc42ae1bd00395
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This patch fixes the nand flash size access issue
found in flash with two logical units
Change-Id: Ifcbaa40709c4ac5d508b629fcc6cf7006f167628
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
This change will read entire ONFI parameter page. This will helpful
while validating new ONFI AVL part.
To read entire ONFI parameter page data structure use command:
"#nand onfipara".
Change-Id: Icea80fce6900716871d8c82a2d1ac0c00531af98
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This device is non onfi device, so adding the device id
and oob information in the nand_ids table.
1.pagesize:2048 bytes
2.oob size:128bytes
3.Ecc:8bits for 512 bytes
4.Manufacturer & device id: 0x98, 0xaC
Change-Id: I43f2ffb33b82b6dbf9da7adbef8e4e93f6d94c87
Signed-off-by: sameeruddin shaik <samesh@codeaurora.org>
This change is to add support for Macronix-(MX25U51245G) nor
flash device.
The total density of this device is 64 MiB. Sector size 64K.
64K sector we are cosidering due to 64K sector size works with
CMD_ERASE_64K.
Total number of sector for this device will 1024 because,
64K * 1024 = 64MiB.
Change-Id: Ia1f2117bc42457e4b3c25934ff1fdcb798e4ea6f
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This change is to add support for Macronix-(MX66U1G45GMI00) nor
flash device.
The total density of this device is 128 MiB. Sector size 64K.
64K sector we are cosidering due to 64K sector size works with
CMD_ERASE_64K.
Total number of sector for this device will 2048 because,
64K * 2048 = 128MiB.
Change-Id: I63bcd4bd5c979a82ca8c45d480acc41208a886ef
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This change will fix the following compiler warnings for AK and DK targets.
1.Wimplicit-function-declaration
2.Wdiscarded-qualifiers
3.Wstrict-prototypes
4.Wmaybe-uninitialized
5.Wunused-variable
6.Wint-conversion
Change-Id: I364904283172ccb19602ae1b6deceb8c61ea7638
Signed-off-by: sameeruddin shaik <samesh@codeaurora.org>
This device is a non onfi device, so adding the device id and
oob details to nand_ids table.
This device is non onfi device, so adding the device id
and oob information in the nand_ids table.
1.pagesize:2048 bytes
2.oob size:128bytes
3.Ecc:8bits for 512 bytes
4.Man & dev id: 0x98 0xa1
Change-Id: I69763ea28fc3f81a74cacad4338b6d55c42d93b6
Signed-off-by: sameeruddin shaik <samesh@codeaurora.org>
Some spi nand flash uses single byte read id(9FH) command,
for those devices the sequence is
byte1 byte2 byte3 byte4
9FH MID DID DID
some other spi nand flashes uses two byte read id(9F 00H) command
for those devices the sequence is
byte1 byte2 byte3 byte4
9FH A7-A0 MID DID
The first byte is the actual command and the second byte is a dummy byte.
For devices which uses new sequence, we need to pass
appropriate read id command with dummy byte.
Change-Id: Idf2e8740f8341596cd8f58d22d5e33a4b4972a31
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
This change modifies kstrtoint function to update
the result in destination buffer and return zero on success.
Change-Id: Ibdd9b36eed39d5e2ee3afc6f1609c1e35d5fb464
Signed-off-by: Pavithra Palanisamy <pavip@codeaurora.org>
Currently, the nand driver expects the start address to be page
aligned. This patch adds the support for reading data from
non-page aligned start address by using intermediate buffer.
1. Determine the number of pages with start address and
length.
2. Do the full page read for all the pages. For first page,
check the start address and determine the column. If column is
non-zero then use the intermediate buffer for page data and copy
the required number of bytes from this intermediate buffer to
actual buffer.
Change-Id: I05a4b98547c83f785096027596cedd83a283edd8
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Currently NAND_CTRL register write generates error.
Register writes to operational registers should always be done
through command descriptors if BAM_MODE is already enabled.
For NAND boot, bootloader already enables BAM_MODE so read the
NAND_CTRL register value and write only if BAM_MODE is not set.
Change-Id: Iabc3e06dc7d8d8b36cdf35907217e1c4d7cc960a
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
If nand id table has specified oobsize then use the same.
Change-Id: I58b19f8f9989c7332d103b83b6920d5b59b29a13
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Following error is coming during UBI mount for non ONFI nand
device since mtd->writebufsize is coming as zero
ubi0: attaching mtd2
UBI init error 22
The mtd->writebufsize is being assigned currently for ONFI
devices only so move this assigment to common place.
Change-Id: Idd22800dd65035952c1afd07ba375a28ffcf76ad
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
The ONFI NAND device specifies the required ECC correction in its
param page but for non ONFI device, we don't have such info.
The QPIC NAND contoller can use 8 bit ECC if the chip has required
number of spare bytes. This patch calculates the minimum required
spare bytes for using 8 bit ECC and select the same, if non ONFI
device has required number of spare bytes otherwise 4 bit ECC
will be used.
Change-Id: If7c718f4288eee16857171335897e3209a05fd0b
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Add the full description of the Toshiba TH58NYG3S0H NAND chip
in the nand_ids table since its spare bytes are coming as 128
instead of 256 with standard calculation. This device is non
ONFI/JEDEC device.
Change-Id: If1938fbcd0ebceb70aa9b620186cc92c6d504f75
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Software SPI reset mode can be trigger from 4-Byte Address mode
in flash W25Q256JW.
Change-Id: I3f8ec46c2732c07a7af0cc7331102334413067ba
Signed-off-by: Santan Kumar <santank@codeaurora.org>
Do generic flash structure initialization, for the devices
not listed in the SPI NOR flash lookup table, so that
we can access the flash even before the support is added.
Block size and density are obtained from smem.
Change-Id: I568eb538615bb36124c43a2509bcfce2e4a1188a
Signed-off-by: Balaji Jagadeesan <bjagadee@codeaurora.org>
When 4K sector size support is enabled for spi, always
4K sector erase command is passed for all the erase operations.
To increase the performance, 64K erase command is
passed to the command buffer based on length and offset.
Change-Id: Ia762d192ba5d424f0ba3538fff8aff4954050bf7
Signed-off-by: Balaji Jagadeesan <bjagadee@codeaurora.org>
This patch adds the support on nand driver to work
when dcache is on.
flush_dcache_range will do both clean and invalidate.
To avoid any data loss when an un-aligned buffer used
in RX path, before giving buffer to bam and after bam
updates the data in buffer, buffer will be flushed.
Change-Id: Ib38d68726efe1692ae94c2be1af61cf29d1c2e50
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Some of the newer nand parts can have bit flips in an erased
page due to the process technology used. In this case, ipq
nand controller is not able to identify that page as an erased
page. In case of bitflips, the ECC engine tries to correct the
data and then it generates the uncorrectable error. Now, this
data is not equal to original raw data.
Following logic is being added to identify the erased
codeword bitflips.
1. Maintain the bitmasks for the codewords which generated
uncorrectable error.
2. Read the raw data again in temp buffer and count the
number of zeros. Since spare bytes are unused in ECC layout and
won’t affect ECC correctability so no need to count number of
zero in spare bytes.
3. If the number of zero is below ECC correctability then it
can be treated as erased CW. In this case, make all the data/oob
of actual user buffers as 0xff.
Change-Id: I5a80cd371a926efa36c40b4db68e78ed78c30536
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Following are the major issues in current implementation
1. The mtd layer expects the driver to return non-negative
integer representing the maximum number of bitflips that were
corrected on any one ecc region. The mtd layer takes care of
returning EUCLEAN based on returned number.
2. The read should return the complete data in case of
EBADMSG so move the EBADMSG check in the main read function.
Change-Id: Iab3a28427e8350e8c99368762373f2cbce918786
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
1. assign ecc strength in mtd structure which will be used by
mtd layer
2. Initialize bitflip_threshold with 3*4 of ecc strength so
that MTD layer will return EUCLEAN if number of ecc correction
are more than bitflip_threshold.
Change-Id: I81cfe6059375117ced7888b877705919287a7be2
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
