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ipq6018: Enabling support for SPI NAND flash "GD5F1GQ4R"

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Change-Id: I8df9be7ca1b8497e018dd563c7522e52a2433cb6
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
This commit is contained in:
Antony Arun T 2018-11-30 15:50:28 +05:30
parent 191aa8b443
commit 0e7bb084f4
1 changed files with 27 additions and 0 deletions
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27
drivers/mtd/spi/spi_nand.c
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@ -34,6 +34,8 @@
#define MACRONIX_NORM_READ_MASK (MACRONIX_WRAP | MACRONIX_PLANE | 0x0F)
#define GIGADEVICE_NORM_READ_MASK 0x0F
#define spi_print(...) printf("spi_nand: " __VA_ARGS__)
struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
@ -42,6 +44,7 @@ int verify_2bit_ecc(int status);
int verify_dummy_ecc(int status);
int verify_2bit_toshiba_ecc(int status);
void gigadevice_norm_read_cmd(u8 *cmd, int column);
void gigadevice_norm_read_cmd_12bit_addr(u8 *cmd, int column);
void macronix_norm_read_cmd(u8 *cmd, int column);
void winbond_norm_read_cmd(u8 *cmd, int column);
void toshiba_norm_read_cmd(u8 *cmd, int column);
@ -67,6 +70,22 @@ static struct spi_nand_flash_params spi_nand_flash_tbl[] = {
.die_select = NULL,
.name = "GD5F1GQ4XC",
},
{
.id = { 0xc8, 0xc1, 0xc8, 0xc1 },
.page_size = 2048,
.erase_size = 0x00020000,
.no_of_dies = 1,
.prev_die_id = INT_MAX,
.pages_per_die = 0x10000,
.pages_per_sector = 64,
.nr_sectors = 1024,
.oob_size = 128,
.protec_bpx = 0xC7,
.norm_read_cmd = gigadevice_norm_read_cmd_12bit_addr,
.verify_ecc = verify_3bit_ecc,
.die_select = NULL,
.name = "GD5F1GQ4R",
},
{
.id = { 0xc8, 0xb4, 0x68, 0xc8 },
.page_size = 4096,
@ -176,6 +195,14 @@ void gigadevice_norm_read_cmd(u8 *cmd, int column)
cmd[3] = (u8)(column);
}
void gigadevice_norm_read_cmd_12bit_addr(u8 *cmd, int column)
{
cmd[0] = IPQ40XX_SPINAND_CMD_NORM_READ;
cmd[1] = ((u8)(column >> 8) & GIGADEVICE_NORM_READ_MASK);
cmd[2] = (u8)(column);
cmd[3] = 0;
}
void macronix_norm_read_cmd(u8 *cmd, int column)
{
cmd[0] = IPQ40XX_SPINAND_CMD_NORM_READ;