Hardware:
- SoC: RTL9313
- Memory: 512MB
- Flash: SPI-NOR 32MB (GigaDevice GD25Q256EFIR)
- Ethernet: 12x 1/2.5/10 Gbps (SFP+)
- LED/Keys (GPIO): 1x/1x
- UART: "Console" port on the front panel
- type: RS-232C
- connector: RJ-45
- settings: 9600n8 / 115200n8
- Watchdog: Diodes PT7A7514WE
- Monitoring: LM75A
- Power: 100-240 VAC 50/60 Hz C13/C14
Important notes:
---------------
* the device uses 9600 Baud by default but this extremely slows down the
device when using the serial console. OpenWrt is configured to use
115200 Baud. If you need to enter the bootloader, you need to use 9600
Baud.
* PT7A7514WE watchdog is fed through hardware-assisted SYS_LED. However,
the bootloader seems to deactivate that again during autoboot. There's
a quirk in early arch setup for this.
* a kernel binary "nos.img" needs to be stored into JFFS2 filesystem
using 4KiB erase block instead of 64KiB.
* V1 is the version with the 19"-sized case. As of 2026, there's a newer
version with a narrow case.
Flash instructions using initramfs image:
-----------------------------------------
(mostly taken from 0dc0b98295)
1. Prepare TFTP server with an IP address in 192.168.2.0/24.
2. Connect your PC to Port 1 on SKS8300-12X.
3. Power on SKS8300-12X and interrupt autoboot by Ctrl + B.
4. Login to the vendor CLI by Ctrl + F and "diagshell_unipoe_env" as password.
5. Switch baudrate to 115200 by running a command and then reconnect
with different settings:
baudrate 115200
6. Switch to U-Boot CLI by "debug_unish_env".
7. Enable Port 1 with the following commands:
rtk 10g 0 fiber1g # (or fiber10g if 10GBase-*R)
rtk ext-devInit 0 # init RTL8231 that holds SFP GPIOs
rtk ext-pinSet 2 0 # set tx-disable of port 1 to LOW
8. Transfer initramfs image via TFTP and boot it:
tftpboot 0x82000000 <serverip>:<image name>
bootm 0x82000000
9. On the initramfs image, backup the stock firmware if needed.
10. Upload (or download) sysupgrade image to the device.
11. Erase "firmware" partition to cleanup JFFS2 of stock FW:
mtd erase firmware
12. Perform sysupgrade with the sysupgrade image.
13. Wait until the flash completes and the system reboots into OpenWrt.
Reverting to stock firmware:
----------------------------
(taken from 0dc0b98295)
1. Prepare OpenWrt SDK to use the mkfs.jffs2 tool contained in it
Note: the official mkfs.jffs2 tool in mtd-utils doesn't support 4KiB
erase size and not usable for SKS8300-8X
2. Create a directory for working
3. Download official firmware for SKS8300-8X from XikeStor's official
website
4. Rename the downloaded firmware to "nos.img" and place it to the
working directory
5. Create a JFFS2 filesystem binary with the working directory
/path/to/mkfs.jffs2 -p -b -U -v -e 4KiB -x lzma \
-o nos.img.jffs2 -d /path/to/working/dir/
6. Upload the created JFFS2 filesystem binary to the device
7. Erase the "firmware" partition
mtd erase firmware
8. Write the JFFS2 filesystem binary to the "firmware" partition
mtd write /path/to/nos.img.jffs2 firmware
9. After writing, reboot the device by power cycle
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21922
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Make xikestor-nosimg a common recipe in the Makefile to allow usage for
other subtargets too, not only rtl930x.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21922
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
On some XikeStor switches (SKS8300-8X, SKS8300-12X), the SYS_LED/GPIO0 is
used to feed an external PT7A7514WE watchdog. While this was no issue on
SKS8300-8X, the bootloader on the SKS8300-12X seems to deactivate the
automatic feeding on purpose by setting the pin function of to GPIO0
instead of SYS_LED. This kills the periodic signal generated on that pin.
This causes the kernel to just stop quite early and reset the system
entirely.
Because this happens very early, it doesn't work to define this as a
pinctrl entry or GPIO hog. The drivers aren't even loaded at that stage.
To work around the issue, we need to configure this in the arch-specific
early setup. An affected device needs to have a corresponding node in
the DTS that is picked up then.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21922
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Use NVMEM in device tree to set the label and eth0 MAC address based on
the U-Boot environment.
Invididual port MAC addresses and bridge MAC are still handled in the
02_network script to maintain the current assignment.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/22055
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This is a preparation to convert some more RTL838x devices to NVMEM.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/22055
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Startup of mdio on a RTL8216 based device currently shows the
following warnings.
[1.948608] skip polling setup for unknown PHY 001ccaf3 on port 0
[1.968920] skip polling setup for unknown PHY 001ccaf3 on port 8
[1.989171] skip polling setup for unknown PHY 001ccaf3 on port 16
[2.009704] skip polling setup for unknown PHY 001ccaf3 on port 20
[2.030209] skip polling setup for unknown PHY 001ccaf3 on port 24
[2.052270] realtek-otto-serdes-mdio 1b000000.switchcore:mdio-serdes:
Realtek SerDes mdio bus initialized, 12 SerDes, 64 pages
Add the phy detection to the mdio bus so that polling setup works.
While we are here sort the phy ids alphabetically.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22109
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Make clearer which field belongs to which register. For this
sort the fields below the registers and use indentation.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22075
Signed-off-by: Robert Marko <robimarko@gmail.com>
PHY polling setup has found a home in the mdio driver. For RTL931x
there still exists a setup sequence for polling type (serdes/mdio)
in the DSA driver. Put it where it belongs.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22075
Signed-off-by: Robert Marko <robimarko@gmail.com>
Get rid of defines that are not used in the driver.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22100
Signed-off-by: Robert Marko <robimarko@gmail.com>
This define is used nowhere. Remove it.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22100
Signed-off-by: Robert Marko <robimarko@gmail.com>
The MAC_FORCE_MODE_CTRL register is only used for the CPU port.
No need to repeat the port register calculation for each usage.
Simply point to the cpu port register directly.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22100
Signed-off-by: Robert Marko <robimarko@gmail.com>
Remove unneeded includes from setup.c and adapt comments.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22084
Signed-off-by: Robert Marko <robimarko@gmail.com>
This allows to drop a family condition check and in the future
allows to merge nowadays splitted functions. While we are here
replace a hardcoded 0xc value with the new value for better
readability.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21999
Signed-off-by: Robert Marko <robimarko@gmail.com>
There is enough info in the control and config structures to derive
the device specific counter freeing. No need to write two different
functions.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21999
Signed-off-by: Robert Marko <robimarko@gmail.com>
Get away with another family check.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21999
Signed-off-by: Robert Marko <robimarko@gmail.com>
During transmit the driver must adapt the packet length. The
hardware requires at least a memory space of ETH_ZLEN bytes
data plus four bytes for layer 2 FCS. This was calculated
(somehow) but skb->len never got updated and for the minimum
length a RTL838x specific workaround was in place. Clean up
the code and use skb_put_padto() so the length change gets
reflected in skb->len.
While we are here drop zeroing DSA tag because it will be
overwritten by hardware for FCS.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21999
Signed-off-by: Robert Marko <robimarko@gmail.com>
Switch from auto-scan PHY discovery to explicit DT-based registration
using fwnode_mdiobus_register_phy(). This is the standard approach used
by of_mdiobus_register() and most MDIO drivers.
Auto-scan (phy_mask-based) registration does not attach DT fwnode data
to PHY devices, which means DT properties like "pses" are never parsed.
As a result, PSE controllers referenced from PHY nodes are not linked,
and ethtool PSE commands (--show-pse, --set-pse) do not work.
Store the device_node for each PHY found during DT parsing, suppress
auto-scan by setting phy_mask to ~0, and register each PHY explicitly
after devm_mdiobus_register(). This allows fwnode_find_pse_control() to
resolve PSE references and also establishes proper fw_devlink supplier
relationships.
Additionally this fixes a bug where the RTL8221B is limited to
1G and below due to missing DTS references.
Fixes: 4e00306 ("realtek: mdio: use bus auto registration")
Signed-off-by: Carlo Szelinsky <github@szelinsky.de>
Link: https://github.com/openwrt/openwrt/pull/22019
Signed-off-by: Robert Marko <robimarko@gmail.com>
No code changes. Just some explanation how these devices
work with physical and logical memory.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22054
Signed-off-by: Robert Marko <robimarko@gmail.com>
Device specific constants belong into the config structure.
No need to initialize them manually during probing within a
family_id switch statement. Although there are lots of constants
that need to be converted start with port_ignore as a simple one.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22026
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add return value to function and add an internal pr_warn().
This simplifies the callers and avoids duplicate coding.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22008
Signed-off-by: Robert Marko <robimarko@gmail.com>
For better readability provide a macro to loop over all
active ports od the mdio bus.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22008
Signed-off-by: Robert Marko <robimarko@gmail.com>
On RTL930x, RTL931x and even RTL838x the smi topology is
configured very similar. There is a bus mapping (RTL930x
and RTL931x) and a port mapping (all three). Define a
common helper that can take care of this setup and call
it before bus registration.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22008
Signed-off-by: Robert Marko <robimarko@gmail.com>
Part of the configuration sequence for 1G operation can be identified as
setting autonegotiation to enabled for that mode. Starting from a previous
commit, this is being handled properly in the set_autoneg implementation.
Thus, remove that part from the sequence which doesn't make sense there
anymore and might just cause problems.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22013
Signed-off-by: Robert Marko <robimarko@gmail.com>
The autonegotiation setting might not have been working for RTL931x the
whole time. While there weren't any reports about issues so far, these
issues might just have been hidden behind other circumstances.
While all other variants of the Otto family have the corresponding
settings in [page 0x2 register 0x0] of a SerDes, RTL931x has a special
Front/Background SerDes architecture and actually moved the
autonegotiation settings to a digital Background SerDes. Since we use a
special mapping to have a consistent view on these Background SerDes,
RTL931x needs to write the settings to another page.
To fix this, adjust the autonegotiation setting for all variants. The
generic implementation is kept but uses per-variant register field
definitions. Those are added for all variants here, with the differing
page for RTL931x.
Another static data definition is renamed since it conflicts with a
change introduced here.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22013
Signed-off-by: Robert Marko <robimarko@gmail.com>
Slight differences between the variants of the Otto family are handled
so far handled using function indirection by defining per-variant
operations which are called from generic implementations. In several
case, this can still be optimized because the variants only differ in
some register addresses and/or bits while the procedure otherwise is
exactly the same.
To address this, add a new SerDes register struct where register fields
can be described and later used by generic implementations which otherwise
would need to be separate just because of slight differences. Add two
register fields for autonegotiation to that register struct which are
used by a successing patch to address a real issue.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22013
Signed-off-by: Robert Marko <robimarko@gmail.com>
We can now setup most of the modes for RTL930x, recently XSGMII, QSGMII
and USXGMII-SX have been added. Thus we don't need a big list of allowed
modes anymore in SerDes setup. Drop this without replacement. Other
modes are still rejected in other places or will be rejected later with
a proper SerDes capability handling.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21930
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add everything that's needed to setup QSGMII mode on the 5G SerDes. This
includes patch sequences, additions to symbol error reset and read, and
allowing this mode during SerDes setup.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21930
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add everything that's needed to setup USXGMII-SX mode (10G single port
USXGMII). This includes patch sequences and adjustments to the symbol
error reset and reading, and allowing it in the SerDes setup.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21930
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
For each port (or port group) the mdio bus needs to define the
PHY type that is attached to it. There are the following bit
values that need to be set in SMI_MAC_TYPE_CTRL.
- 0x0: 10G/1G Fiber (SerDes)
- 0x1: 10G/2G5 GPHY
- 0x2: FEPHY
- 0x3: GPHY
SerDes ports are out of scope of the mdio driver and are handled
by the PCS driver. So the corresponding bits are untouched. That
is not good as the register default is 0x3 for ports 0-23. To
make it simple: Without proper setup devices that have SerDes
driven fiber ports at address 0-23 do not poll in the right way.
Link detection is broken.
Fix this by initializing the register to zero. This way all ports
that are not setup by the mdio driver default to "SerDes". That
should be a reasonable assumption.
Fixes: b271735 ("realtek: mdio: Simplify RTL930x phy polling setup")
Reported-by: Joe Holden <jwh@zorins.us>
Suggested-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22032
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
These devices contain a single MAC address in the U-Boot environment.
Set it as eth0 and label MAC in device tree.
To maintain the current state, the 02_network script still sets
individual port MAC addresses and the bridge MAC address.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/22024
Signed-off-by: Robert Marko <robimarko@gmail.com>
Fix the function for reading the SerDes link status to work correctly
based on the code the SDK uses. This is mostly for the sake of
documentation and quick access to the information. The function isn't
used currently but may be in the future, thus no functional change here.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22014
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add 2500Base-X handling to mode setting which was rejected with
-ENOTSUPP before. SDK code available to us doesn't have the proper mode
value. Though by brute-forcing different mode values, 0x2d was found to
make a 2500Base-X link work.
This was tested with an otherwise correctly configured RTL8221B PHY
which is automatically switched between 2500Base-X and SGMII in the
upstream driver. Though, since there was a previous U-Boot setup for the
PHY in HISGMII mode, it may not be standalone yet.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22014
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Move the function into the config area to avoid family checks.
While we are here apply the new dsa function prefix.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22009
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Right now the global includes are all named rtl838x. This suggests
that they are only for one of the four SoC types (RTL838x aka Maple)
required. As we are talking about the Otto platform rename that
accordingly. All the drivers have already adapted that some time
ago.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22005
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add support for V2 of Zyxel GS1920-24HP with 24 copper ports, 4 combo
SFP/copper ports and PoE.
Specifications:
---------------
* SoC: Realtek RTL8391M
* Flash: 32MiB Flash
* RAM: 256MiB
* Ethernet: 24x 10/100/1000 Mbps
* SFP: 4 combo copper/SFP ports (via RTL8214FC)
* PoE: 24x
* Fan controller: ADT7468
* Serial: UART 3.3V TTL logic, 115200 8N1
* pinout (front to back): GND RX TX VCC
* Buttons: 1x Reset, 1x Restore
Notable differences to V1 (which require dedicated support):
* "smaller" SoC (RTL8391M)
* more RAM (256MiB vs 128MiB)
* more Flash (32MiB vs 16MiB) + different layout
* RTL8214FC uses different port numbers
* SFP 25 and 26 use shared SCL
* SFP 27 and 28 use different SDA
* different monitoring IC (LM96000 vs ADT7468)
* faster serial console by default
* serial header easier accessible
Note that the port LEDs do not work correctly yet due to missing
LED configuration for RTL839X.
Installation:
-------------
(copied mostly as-is from 2a55846bf4)
This device uses ZyNOS instead of Linux, this makes installation a bit
more cumbersome. Serial console is required!
1. Set the switch to boot from the first image. This step is crucial,
it will fail to boot if this is not set properly.
2. Connect to the switch using serial and interrupt the boot process
to enter debug/recovery mode.
3. Load the OpenWrt initramfs image via XMODEM. You need to obtain an
unlock code, based on your MAC address, first. See the excellent write
up at https://www.ixo.de/info/zyxel_uclinux/ for details. Replace
unlock_code in the commands below by the code obtained.
The file length in bytes needs to be given instead of file_length below.
You also need an XMODEM upload utility like "lrzsz-sx -X" to transfer
the file. Start the XMODEM upload after running the ATUPxxxx command:
> ATEN1,unlock_code
> ATUP80100000,file_length
> ATGO80100000
4. Wait for OpenWrt to boot. Once this is done, transfer the loader binary
and the sysupgrade image to "/tmp" using scp.
5. Install OpenWrt permanently by running the following two commands on
the switch (over SSH):
> mtd write /tmp/loader.bin loader
> mtd write /tmp/sysupgrade.bin firmware
6. Reboot the switch and enjoy OpenWrt.
NB: You do not need to touch the loader binary unless it's recommended.
The loader is not part of a regular sysupgrade file and will be left
untouched. The boot loader only checks if the loader is valid to be
able to boot.
Recovery/ Return to stock:
--------------------------
Just spam the "u" key during (or "z" for 9600 baud) during memory testing
to trigger a recovery XMODEM upload at 115200 baud. A standard OEM upgrade
image works properly.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21944
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Move common parts shared with GS1920-24HPv2 from v1's DTS and image
definition into a common DTSI and device definition to prepare adding
support for GS1920-24HPv2.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21944
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Global interrupt enabling/disabling is scattered around the code. Provide
two helpers to handle this code centrally. Make use of them where needed.
This refactoring brings multiple enhancements:
1. Only activate the rx interrupts and ignore the run out (aka rx overflow)
interrupts. Overflow was used to spit out log messages to identify driver
issues. Nowadays it is stable enough and these messages are not needed
any longer.
2. With generic register setting some family checks can be dropped.
3. Last but not least this commit fixes a bug in the probing of the ethernet
driver. In rare case (especially during TFTP boot) U-Boot loader leaves a
pending rx interrupt that instantly fires when the driver registers its
interrupt via devm_request_irq(). To mitigate this, reorder the interrupt
disabling from ndo_open() to driver probing.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21893
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Regardless of the number of receive queues (8 or 32) the interrupt
status and mask registers are built up bitwise in the same way:
- 8/32 rx run out interrupts
- 8/32 rx done interrupts
- 2 tx tone interrupts
- 2 tx all done interrupts
- 3 L2 notify interrupts (only RTL839x)
So one can always derive the bit position of those fields by using
the device specific rx_rings configuration setting. To simplify the
code these registers will be handled by central helpers in the future.
In a first step provide a interrupt base register definition that
points to the first interrupt type - aka the rx run out interrupts.
To not overcomplicate things simply reuse the existing DMA_IF_INTR_MSK
and DMA_IF_INTR_STS naming convention. Until all gets fixed the
runout registers on RTL93xx will be accessible by that name.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21893
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Do better error checks during bus probing. Give meaningful return codes
in case of invalid DTS data (EINVAL instead of ENODEV). Decrease node
reference in case of errors.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21968
Signed-off-by: Robert Marko <robimarko@gmail.com>
The mdio bus no longer mixes reset and polling setup. There is now
a clear distinction between both parts and polling setup can rely
on an initialized bus. With that in place skip the open coded phy
detection and use standard kernel functions instead.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21968
Signed-off-by: Robert Marko <robimarko@gmail.com>
Let the mdio bus autodetect the attached phys by providing a proper
scan mask. Although this breaks the linkage to the DTS it is better
than adding phys manually.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21968
Signed-off-by: Robert Marko <robimarko@gmail.com>
The mdio bus detection will be changed from DTS based detection to
autoscan. To avoid spurious WARN_ONCE() messages return -EIO for
reads to register 2 during C22 scan when phy is on a c45 based bus.
The C45 rescan afterwards will detect the phy normally.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21968
Signed-off-by: Robert Marko <robimarko@gmail.com>
Now that reset() and setup_polling() functions are split, clarify the
documentation about the C22/C45 register setup. It is important for
all phy accesses and must be configured during reset. Of course a side
effect is, that the SoC adapts its polling.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21968
Signed-off-by: Robert Marko <robimarko@gmail.com>
The reset function of the RTL838x mdio bus does not only reset
things but sets up polling parameters too. Split this function.
While we are here give an anonymous bit a meaningful name.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21968
Signed-off-by: Robert Marko <robimarko@gmail.com>
There is a misunderstanding of the chip version detection in the
rt-loader. For all SoCs the data is gathered from the registers
MODEL_NAME_INFO and CHIP_INFO. Sadly the bits are shuffled around
with each hardware. Currently the loader gathers the wrong bits
for RTL839x and RTL93xx. Fix that.
While we are here write the if statements vice versa for better
readability and give some variables better names. Align the
ouput with that from the kernel.
Fixes: ccbff8b ("realtek: add rt-loader (runtime loader)"
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21994
Signed-off-by: Robert Marko <robimarko@gmail.com>
The MAC addresses for eth0 and the individual LAN ports are now
configured via device tree. The assignment itself stays the same as
before, matching factory firmware.
The 02_network script still sets the bridge MAC address, as it is
different from the lowest port MAC address.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/21976
Signed-off-by: Robert Marko <robimarko@gmail.com>
SerDes attached ports that are connected during switch
boot might not be able to transmit any data after SerDes
setup. Especially ports that passed traffic before (e.g.
for tftp initramfs boot) seem to be affected. Ports that
are connected later do not show this issue.
It turns out that the old SerDes setup never really worked
on RTL8382 and the pcs refactoring (with dynamic SerDes
start and stop) totally changed the order of network bringup
in contrast to Realtek SDK.
Fix this by restaring the switch queue whenever a SerDes
goes up for the first time.
Fixes: e956adf ("realtek: rtl838x: setup SDS in PCS driver")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21956
Signed-off-by: Robert Marko <robimarko@gmail.com>
The write protection register (0x1b000058) is opened up in prom init
but closed later in rtl838x_pie_init(). From that moment no more
special register writes are possible.
Only unlock the write protection register once during prom init.
Remove all other references. The error has been active since ages
but was not visible until pcs refactoring. For reference blame the
refactoring commit.
Fixes: e956adf ("realtek: rtl838x: setup SDS entirely in PCS driver")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21956
Signed-off-by: Robert Marko <robimarko@gmail.com>
