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realtek: eth: simplify MAC_FORCE_MODE_CTRL usage

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The MAC_FORCE_MODE_CTRL register is only used for the CPU port.
No need to repeat the port register calculation for each usage.
Simply point to the cpu port register directly.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22100
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Markus Stockhausen 2026-02-19 21:22:58 +01:00 • committed by Robert Marko
parent 2256cfac68
commit ee7ff1e8b0
2 changed files with 21 additions and 23 deletions
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26
target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c
View file

@ -594,7 +594,7 @@ static void rtl838x_hw_en_rxtx(struct rteth_ctrl *ctrl)
* | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
* | MEDIA_SEL
*/
sw_w32(0x6192F, ctrl->r->mac_force_mode_ctrl + ctrl->r->cpu_port * 4);
sw_w32(0x6192F, ctrl->r->mac_force_mode_ctrl);
/* Enable CRC checks on CPU-port */
sw_w32_mask(0, BIT(3), ctrl->r->mac_l2_port_ctrl);
@ -620,7 +620,7 @@ static void rtl839x_hw_en_rxtx(struct rteth_ctrl *ctrl)
sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL);
/* Force CPU port link up */
sw_w32_mask(0, 3, ctrl->r->mac_force_mode_ctrl + ctrl->r->cpu_port * 4);
sw_w32_mask(0, 3, ctrl->r->mac_force_mode_ctrl);
}
static void rtl93xx_hw_en_rxtx(struct rteth_ctrl *ctrl)
@ -654,9 +654,9 @@ static void rtl93xx_hw_en_rxtx(struct rteth_ctrl *ctrl)
sw_w32_mask(0, BIT(ctrl->r->cpu_port), RTL931X_L2_UNKN_UC_FLD_PMSK);
if (ctrl->r->family_id == RTL9300_FAMILY_ID)
sw_w32(0x217, ctrl->r->mac_force_mode_ctrl + ctrl->r->cpu_port * 4);
sw_w32(0x217, ctrl->r->mac_force_mode_ctrl);
else
sw_w32(0x2a1d, ctrl->r->mac_force_mode_ctrl + ctrl->r->cpu_port * 4);
sw_w32(0x2a1d, ctrl->r->mac_force_mode_ctrl);
}
static void rteth_setup_ring_buffer(struct rteth_ctrl *ctrl)
@ -819,11 +819,11 @@ static void rtl838x_hw_stop(struct rteth_ctrl *ctrl)
/* CPU-Port: Link down */
if (ctrl->r->family_id == RTL8380_FAMILY_ID || ctrl->r->family_id == RTL8390_FAMILY_ID)
sw_w32(force_mac, ctrl->r->mac_force_mode_ctrl + ctrl->r->cpu_port * 4);
sw_w32(force_mac, ctrl->r->mac_force_mode_ctrl);
else if (ctrl->r->family_id == RTL9300_FAMILY_ID)
sw_w32_mask(0x3, 0, ctrl->r->mac_force_mode_ctrl + ctrl->r->cpu_port * 4);
sw_w32_mask(0x3, 0, ctrl->r->mac_force_mode_ctrl);
else if (ctrl->r->family_id == RTL9310_FAMILY_ID)
sw_w32_mask(BIT(0) | BIT(9), 0, ctrl->r->mac_force_mode_ctrl + ctrl->r->cpu_port * 4);
sw_w32_mask(BIT(0) | BIT(9), 0, ctrl->r->mac_force_mode_ctrl);
mdelay(100);
rteth_disable_all_irqs(ctrl);
@ -1157,9 +1157,9 @@ static void rteth_pcs_an_restart(struct phylink_pcs *pcs)
pr_debug("In %s\n", __func__);
/* Restart by disabling and re-enabling link */
sw_w32(0x6192D, ctrl->r->mac_force_mode_ctrl + ctrl->r->cpu_port * 4);
sw_w32(0x6192D, ctrl->r->mac_force_mode_ctrl);
mdelay(20);
sw_w32(0x6192F, ctrl->r->mac_force_mode_ctrl + ctrl->r->cpu_port * 4);
sw_w32(0x6192F, ctrl->r->mac_force_mode_ctrl);
}
static void rteth_pcs_get_state(struct phylink_pcs *pcs,
@ -1427,7 +1427,7 @@ static const struct rteth_config rteth_838x_cfg = {
.dma_if_intr_sts = RTETH_838X_DMA_IF_INTR_STS,
.dma_if_intr_msk = RTETH_838X_DMA_IF_INTR_MSK,
.dma_if_ctrl = RTL838X_DMA_IF_CTRL,
.mac_force_mode_ctrl = RTL838X_MAC_FORCE_MODE_CTRL,
.mac_force_mode_ctrl = RTETH_838X_MAC_FORCE_MODE_CTRL,
.dma_rx_base = RTL838X_DMA_RX_BASE,
.dma_tx_base = RTL838X_DMA_TX_BASE,
.dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size,
@ -1476,7 +1476,7 @@ static const struct rteth_config rteth_839x_cfg = {
.dma_if_intr_sts = RTETH_839X_DMA_IF_INTR_STS,
.dma_if_intr_msk = RTETH_839X_DMA_IF_INTR_MSK,
.dma_if_ctrl = RTL839X_DMA_IF_CTRL,
.mac_force_mode_ctrl = RTL839X_MAC_FORCE_MODE_CTRL,
.mac_force_mode_ctrl = RTETH_839X_MAC_FORCE_MODE_CTRL,
.dma_rx_base = RTL839X_DMA_RX_BASE,
.dma_tx_base = RTL839X_DMA_TX_BASE,
.dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size,
@ -1530,7 +1530,7 @@ static const struct rteth_config rteth_930x_cfg = {
.l2_ntfy_if_intr_sts = RTL930X_L2_NTFY_IF_INTR_STS,
.l2_ntfy_if_intr_msk = RTL930X_L2_NTFY_IF_INTR_MSK,
.dma_if_ctrl = RTL930X_DMA_IF_CTRL,
.mac_force_mode_ctrl = RTL930X_MAC_FORCE_MODE_CTRL,
.mac_force_mode_ctrl = RTETH_930X_MAC_FORCE_MODE_CTRL,
.dma_rx_base = RTL930X_DMA_RX_BASE,
.dma_tx_base = RTL930X_DMA_TX_BASE,
.dma_if_rx_ring_size = rtl930x_dma_if_rx_ring_size,
@ -1583,7 +1583,7 @@ static const struct rteth_config rteth_931x_cfg = {
.l2_ntfy_if_intr_sts = RTL931X_L2_NTFY_IF_INTR_STS,
.l2_ntfy_if_intr_msk = RTL931X_L2_NTFY_IF_INTR_MSK,
.dma_if_ctrl = RTL931X_DMA_IF_CTRL,
.mac_force_mode_ctrl = RTL931X_MAC_FORCE_MODE_CTRL,
.mac_force_mode_ctrl = RTETH_931X_MAC_FORCE_MODE_CTRL,
.dma_rx_base = RTL931X_DMA_RX_BASE,
.dma_tx_base = RTL931X_DMA_TX_BASE,
.dma_if_rx_ring_size = rtl931x_dma_if_rx_ring_size,

18
target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.h
View file

@ -8,6 +8,8 @@
#define RTETH_838X_CPU_PORT 28
#define RTETH_838X_DMA_IF_INTR_MSK (0x9f50)
#define RTETH_838X_DMA_IF_INTR_STS (0x9f54)
#define RTETH_838X_MAC_FORCE_MODE_CTRL (0xa104 + RTETH_838X_CPU_PORT * 4)
#define RTETH_838X_MAC_L2_PORT_CTRL (0xd560 + RTETH_838X_CPU_PORT * 128)
#define RTETH_838X_QM_PKT2CPU_INTPRI_MAP (0x5f10)
#define RTETH_838X_QM_PKT2CPU_INTPRI_0 (0x5f04)
#define RTETH_838X_QM_PKT2CPU_INTPRI_CNT 3
@ -15,6 +17,8 @@
#define RTETH_839X_CPU_PORT 52
#define RTETH_839X_DMA_IF_INTR_MSK (0x7864)
#define RTETH_839X_DMA_IF_INTR_STS (0x7868)
#define RTETH_839X_MAC_FORCE_MODE_CTRL (0x02bc + RTETH_839X_CPU_PORT * 4)
#define RTETH_839X_MAC_L2_PORT_CTRL (0x8004 + RTETH_839X_CPU_PORT * 128)
#define RTETH_839X_QM_PKT2CPU_INTPRI_MAP (0x1154)
#define RTETH_839X_QM_PKT2CPU_INTPRI_0 (0x1148)
#define RTETH_839X_QM_PKT2CPU_INTPRI_CNT 3
@ -22,12 +26,16 @@
#define RTETH_930X_CPU_PORT 28
#define RTETH_930X_DMA_IF_INTR_MSK (0xe010)
#define RTETH_930X_DMA_IF_INTR_STS (0xe01c)
#define RTETH_930X_MAC_FORCE_MODE_CTRL (0xca1c + RTETH_930X_CPU_PORT * 4)
#define RTETH_930X_MAC_L2_PORT_CTRL (0x3268 + RTETH_930X_CPU_PORT * 64)
#define RTETH_930X_QM_RSN2CPUQID_CTRL_0 (0xa344)
#define RTETH_930X_QM_RSN2CPUQID_CTRL_CNT 11
#define RTETH_931X_CPU_PORT 56
#define RTETH_931X_DMA_IF_INTR_MSK (0x0910)
#define RTETH_931X_DMA_IF_INTR_STS (0x091c)
#define RTETH_931X_MAC_FORCE_MODE_CTRL (0x0dcc + RTETH_931X_CPU_PORT * 4)
#define RTETH_931X_MAC_L2_PORT_CTRL (0x6000 + RTETH_931X_CPU_PORT * 128)
#define RTETH_931X_QM_RSN2CPUQID_CTRL_0 (0xa9f4)
#define RTETH_931X_QM_RSN2CPUQID_CTRL_CNT 14
@ -50,11 +58,6 @@
* for all targets.
*/
#define RTETH_838X_MAC_L2_PORT_CTRL (0xd560 + (RTETH_838X_CPU_PORT << 7))
#define RTETH_839X_MAC_L2_PORT_CTRL (0x8004 + (RTETH_839X_CPU_PORT << 7))
#define RTETH_930X_MAC_L2_PORT_CTRL (0x3268 + (RTETH_930X_CPU_PORT << 6))
#define RTETH_931X_MAC_L2_PORT_CTRL (0x6000 + (RTETH_931X_CPU_PORT << 7))
/* DMA interrupt control and status registers */
#define RTL838X_DMA_IF_CTRL (0x9f58)
@ -77,11 +80,6 @@
#define RTL931X_L2_NTFY_IF_INTR_MSK (0x09E4)
#define RTL931X_L2_NTFY_IF_INTR_STS (0x09E8)
#define RTL838X_MAC_FORCE_MODE_CTRL (0xa104)
#define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc)
#define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
#define RTL931X_MAC_FORCE_MODE_CTRL (0x0dcc)
#define RTL839X_DMA_IF_INTR_NOTIFY_MASK GENMASK(22, 20)
#define RTL83XX_DMA_IF_INTR_RX_DONE_MASK GENMASK(15, 8)
#define RTL83XX_DMA_IF_INTR_RX_RUN_OUT_MASK GENMASK(7, 0)