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realtek: eth: define interrupt status/mask base
Regardless of the number of receive queues (8 or 32) the interrupt status and mask registers are built up bitwise in the same way: - 8/32 rx run out interrupts - 8/32 rx done interrupts - 2 tx tone interrupts - 2 tx all done interrupts - 3 L2 notify interrupts (only RTL839x) So one can always derive the bit position of those fields by using the device specific rx_rings configuration setting. To simplify the code these registers will be handled by central helpers in the future. In a first step provide a interrupt base register definition that points to the first interrupt type - aka the rx run out interrupts. To not overcomplicate things simply reuse the existing DMA_IF_INTR_MSK and DMA_IF_INTR_STS naming convention. Until all gets fixed the runout registers on RTL93xx will be accessible by that name. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/21893 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Markus Stockhausen
Hauke Mehrtens
parent
db91c68233
commit
f617d3e594
2 changed files with 24 additions and 26 deletions
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@ -401,7 +401,7 @@ static irqreturn_t rteth_93xx_net_irq(int irq, void *dev_id)
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{
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struct net_device *dev = dev_id;
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struct rteth_ctrl *ctrl = netdev_priv(dev);
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u32 status_rx_r = sw_r32(ctrl->r->dma_if_intr_rx_runout_sts);
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u32 status_rx_r = sw_r32(ctrl->r->dma_if_intr_sts);
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u32 status_rx = sw_r32(ctrl->r->dma_if_intr_rx_done_sts);
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u32 status_tx = sw_r32(ctrl->r->dma_if_intr_tx_done_sts);
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@ -432,8 +432,8 @@ static irqreturn_t rteth_93xx_net_irq(int irq, void *dev_id)
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/* RX buffer overrun */
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if (status_rx_r) {
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pr_debug("RX buffer overrun: status %x, mask: %x\n",
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status_rx_r, sw_r32(ctrl->r->dma_if_intr_rx_runout_msk));
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sw_w32(status_rx_r, ctrl->r->dma_if_intr_rx_runout_sts);
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status_rx_r, sw_r32(ctrl->r->dma_if_intr_msk));
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sw_w32(status_rx_r, ctrl->r->dma_if_intr_sts);
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}
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return IRQ_HANDLED;
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@ -500,8 +500,8 @@ static void rteth_839x_hw_reset(struct rteth_ctrl *ctrl)
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static void rteth_93xx_hw_reset(struct rteth_ctrl *ctrl)
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{
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/* Disable and clear interrupts */
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sw_w32(0x00000000, ctrl->r->dma_if_intr_rx_runout_msk);
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sw_w32(0xffffffff, ctrl->r->dma_if_intr_rx_runout_sts);
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sw_w32(0x00000000, ctrl->r->dma_if_intr_msk);
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sw_w32(0xffffffff, ctrl->r->dma_if_intr_sts);
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sw_w32(0x00000000, ctrl->r->dma_if_intr_rx_done_msk);
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sw_w32(0xffffffff, ctrl->r->dma_if_intr_rx_done_sts);
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sw_w32(0x00000000, ctrl->r->dma_if_intr_tx_done_msk);
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@ -641,7 +641,7 @@ static void rtl93xx_hw_en_rxtx(struct rteth_ctrl *ctrl)
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}
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/* Enable Notify, RX done and RX overflow, TX done interrupts not needed */
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sw_w32(0xffffffff, ctrl->r->dma_if_intr_rx_runout_msk);
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sw_w32(0xffffffff, ctrl->r->dma_if_intr_msk);
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sw_w32(0xffffffff, ctrl->r->dma_if_intr_rx_done_msk);
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sw_w32(0x00000000, ctrl->r->dma_if_intr_tx_done_msk);
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@ -835,8 +835,8 @@ static void rtl838x_hw_stop(struct rteth_ctrl *ctrl)
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/* Disable all TX/RX interrupts */
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if (ctrl->r->family_id == RTL9300_FAMILY_ID || ctrl->r->family_id == RTL9310_FAMILY_ID) {
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sw_w32(0x00000000, ctrl->r->dma_if_intr_rx_runout_msk);
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sw_w32(0xffffffff, ctrl->r->dma_if_intr_rx_runout_sts);
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sw_w32(0x00000000, ctrl->r->dma_if_intr_msk);
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sw_w32(0xffffffff, ctrl->r->dma_if_intr_sts);
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sw_w32(0x00000000, ctrl->r->dma_if_intr_rx_done_msk);
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sw_w32(0xffffffff, ctrl->r->dma_if_intr_rx_done_sts);
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sw_w32(0x00000000, ctrl->r->dma_if_intr_tx_done_msk);
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@ -1449,8 +1449,8 @@ static const struct rteth_config rteth_838x_cfg = {
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.qm_pkt2cpu_intpri_map = RTETH_838X_QM_PKT2CPU_INTPRI_MAP,
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.qm_rsn2cpuqid_ctrl = RTETH_838X_QM_PKT2CPU_INTPRI_0,
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.qm_rsn2cpuqid_cnt = RTETH_838X_QM_PKT2CPU_INTPRI_CNT,
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.dma_if_intr_sts = RTL838X_DMA_IF_INTR_STS,
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.dma_if_intr_msk = RTL838X_DMA_IF_INTR_MSK,
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.dma_if_intr_sts = RTETH_838X_DMA_IF_INTR_STS,
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.dma_if_intr_msk = RTETH_838X_DMA_IF_INTR_MSK,
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.dma_if_ctrl = RTL838X_DMA_IF_CTRL,
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.mac_force_mode_ctrl = RTL838X_MAC_FORCE_MODE_CTRL,
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.dma_rx_base = RTL838X_DMA_RX_BASE,
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@ -1496,8 +1496,8 @@ static const struct rteth_config rteth_839x_cfg = {
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.qm_pkt2cpu_intpri_map = RTETH_839X_QM_PKT2CPU_INTPRI_MAP,
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.qm_rsn2cpuqid_ctrl = RTETH_839X_QM_PKT2CPU_INTPRI_0,
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.qm_rsn2cpuqid_cnt = RTETH_839X_QM_PKT2CPU_INTPRI_CNT,
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.dma_if_intr_sts = RTL839X_DMA_IF_INTR_STS,
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.dma_if_intr_msk = RTL839X_DMA_IF_INTR_MSK,
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.dma_if_intr_sts = RTETH_839X_DMA_IF_INTR_STS,
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.dma_if_intr_msk = RTETH_839X_DMA_IF_INTR_MSK,
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.dma_if_ctrl = RTL839X_DMA_IF_CTRL,
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.mac_force_mode_ctrl = RTL839X_MAC_FORCE_MODE_CTRL,
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.dma_rx_base = RTL839X_DMA_RX_BASE,
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@ -1542,10 +1542,10 @@ static const struct rteth_config rteth_930x_cfg = {
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.mac_l2_port_ctrl = RTETH_930X_MAC_L2_PORT_CTRL,
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.qm_rsn2cpuqid_ctrl = RTETH_930X_QM_RSN2CPUQID_CTRL_0,
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.qm_rsn2cpuqid_cnt = RTETH_930X_QM_RSN2CPUQID_CTRL_CNT,
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.dma_if_intr_rx_runout_sts = RTL930X_DMA_IF_INTR_RX_RUNOUT_STS,
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.dma_if_intr_sts = RTETH_930X_DMA_IF_INTR_STS,
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.dma_if_intr_rx_done_sts = RTL930X_DMA_IF_INTR_RX_DONE_STS,
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.dma_if_intr_tx_done_sts = RTL930X_DMA_IF_INTR_TX_DONE_STS,
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.dma_if_intr_rx_runout_msk = RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK,
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.dma_if_intr_msk = RTETH_930X_DMA_IF_INTR_MSK,
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.dma_if_intr_rx_done_msk = RTL930X_DMA_IF_INTR_RX_DONE_MSK,
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.dma_if_intr_tx_done_msk = RTL930X_DMA_IF_INTR_TX_DONE_MSK,
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.l2_ntfy_if_intr_sts = RTL930X_L2_NTFY_IF_INTR_STS,
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@ -1593,10 +1593,10 @@ static const struct rteth_config rteth_931x_cfg = {
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.mac_l2_port_ctrl = RTETH_931X_MAC_L2_PORT_CTRL,
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.qm_rsn2cpuqid_ctrl = RTETH_931X_QM_RSN2CPUQID_CTRL_0,
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.qm_rsn2cpuqid_cnt = RTETH_931X_QM_RSN2CPUQID_CTRL_CNT,
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.dma_if_intr_rx_runout_sts = RTL931X_DMA_IF_INTR_RX_RUNOUT_STS,
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.dma_if_intr_sts = RTETH_931X_DMA_IF_INTR_STS,
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.dma_if_intr_rx_done_sts = RTL931X_DMA_IF_INTR_RX_DONE_STS,
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.dma_if_intr_tx_done_sts = RTL931X_DMA_IF_INTR_TX_DONE_STS,
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.dma_if_intr_rx_runout_msk = RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK,
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.dma_if_intr_msk = RTETH_931X_DMA_IF_INTR_MSK,
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.dma_if_intr_rx_done_msk = RTL931X_DMA_IF_INTR_RX_DONE_MSK,
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.dma_if_intr_tx_done_msk = RTL931X_DMA_IF_INTR_TX_DONE_MSK,
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.l2_ntfy_if_intr_sts = RTL931X_L2_NTFY_IF_INTR_STS,
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@ -6,20 +6,28 @@
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/* Register definition */
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#define RTETH_838X_CPU_PORT 28
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#define RTETH_838X_DMA_IF_INTR_MSK (0x9f50)
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#define RTETH_838X_DMA_IF_INTR_STS (0x9f54)
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#define RTETH_838X_QM_PKT2CPU_INTPRI_MAP (0x5f10)
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#define RTETH_838X_QM_PKT2CPU_INTPRI_0 (0x5f04)
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#define RTETH_838X_QM_PKT2CPU_INTPRI_CNT 3
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#define RTETH_839X_CPU_PORT 52
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#define RTETH_839X_DMA_IF_INTR_MSK (0x7864)
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#define RTETH_839X_DMA_IF_INTR_STS (0x7868)
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#define RTETH_839X_QM_PKT2CPU_INTPRI_MAP (0x1154)
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#define RTETH_839X_QM_PKT2CPU_INTPRI_0 (0x1148)
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#define RTETH_839X_QM_PKT2CPU_INTPRI_CNT 3
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#define RTETH_930X_CPU_PORT 28
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#define RTETH_930X_DMA_IF_INTR_MSK (0xe010)
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#define RTETH_930X_DMA_IF_INTR_STS (0xe01c)
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#define RTETH_930X_QM_RSN2CPUQID_CTRL_0 (0xa344)
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#define RTETH_930X_QM_RSN2CPUQID_CTRL_CNT 11
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#define RTETH_931X_CPU_PORT 56
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#define RTETH_931X_DMA_IF_INTR_MSK (0x0910)
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#define RTETH_931X_DMA_IF_INTR_STS (0x091c)
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#define RTETH_931X_QM_RSN2CPUQID_CTRL_0 (0xa9f4)
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#define RTETH_931X_QM_RSN2CPUQID_CTRL_CNT 14
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@ -49,18 +57,12 @@
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/* DMA interrupt control and status registers */
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#define RTL838X_DMA_IF_CTRL (0x9f58)
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#define RTL838X_DMA_IF_INTR_STS (0x9f54)
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#define RTL838X_DMA_IF_INTR_MSK (0x9f50)
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#define RTL839X_DMA_IF_CTRL (0x786c)
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#define RTL839X_DMA_IF_INTR_STS (0x7868)
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#define RTL839X_DMA_IF_INTR_MSK (0x7864)
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#define RTL930X_DMA_IF_CTRL (0xe028)
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#define RTL930X_DMA_IF_INTR_RX_RUNOUT_STS (0xe01C)
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#define RTL930X_DMA_IF_INTR_RX_DONE_STS (0xe020)
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#define RTL930X_DMA_IF_INTR_TX_DONE_STS (0xe024)
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#define RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK (0xe010)
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#define RTL930X_DMA_IF_INTR_RX_DONE_MSK (0xe014)
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#define RTL930X_DMA_IF_INTR_TX_DONE_MSK (0xe018)
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#define RTL930X_L2_NTFY_IF_INTR_MSK (0xe04C)
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@ -68,10 +70,8 @@
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/* TODO: RTL931X_DMA_IF_CTRL has different bits meanings */
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#define RTL931X_DMA_IF_CTRL (0x0928)
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#define RTL931X_DMA_IF_INTR_RX_RUNOUT_STS (0x091c)
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#define RTL931X_DMA_IF_INTR_RX_DONE_STS (0x0920)
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#define RTL931X_DMA_IF_INTR_TX_DONE_STS (0x0924)
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#define RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK (0x0910)
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#define RTL931X_DMA_IF_INTR_RX_DONE_MSK (0x0914)
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#define RTL931X_DMA_IF_INTR_TX_DONE_MSK (0x0918)
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#define RTL931X_L2_NTFY_IF_INTR_MSK (0x09E4)
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@ -429,10 +429,8 @@ struct rteth_config {
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int qm_rsn2cpuqid_cnt;
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int dma_if_intr_sts;
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int dma_if_intr_msk;
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int dma_if_intr_rx_runout_sts;
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int dma_if_intr_rx_done_sts;
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int dma_if_intr_tx_done_sts;
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int dma_if_intr_rx_runout_msk;
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int dma_if_intr_rx_done_msk;
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int dma_if_intr_tx_done_msk;
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int l2_ntfy_if_intr_sts;
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