Flash Status register value will get updated in [15:8]
bits section. Hence right shift first and then extract
the required bit value.
Change-Id: I7f2233f22984da3db2324e9e2ba8aafff76adb32
Signed-off-by: Kavin A <quic_kavia@quicinc.com>
Winbond SPI Nand devices provides two different modes for read operations,
Buffer Read Mode (BUF=1) and Continuous Read Mode (BUF=0).
We can configure the BUF bit to read and operate in any one mode.
Change-Id: Ie7adce70642756725e52dab8821333c42fdb601f
Signed-off-by: Kavin A <quic_kavia@quicinc.com>
This change will add support for Winbond "W25N01GWZEIG" spi nand
Change-Id: Ic42938142115408406a8790e114d2d2acfc0dbb5
Signed-off-by: Kavin A <quic_kavia@quicinc.com>
This change will add support for Macronix "MX35UF2GE4AD-Z4I" spi nand
Change-Id: I5d783473c0ec918b02e59a85b71ee941fe649365
Signed-off-by: Kavin A <quic_kavia@quicinc.com>
qpic_nand sbl -> to switch to 2K layout
qpic_nand linux -> to switch back to 4K layout
Currently this switch is enabled for IPQ9574
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
(cherry picked from commit c9a1c10b2e35ba8f14dafc1f4c07aa5a07a01541)
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Change-Id: I3e429b8cd5e600b4214c01d7949c01536f988e47
This change will add support for 4K Macronix spi nand
"MX35UF4GE4AD-Z4I"
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Change-Id: I94e07d9e25de46c67fcb679ef149990e093afc8f
This change will add support for Macronix "MX35UF1GE4AC" spi nand
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I66e82e22217d655b44e30baa64f3aefd5a5f2aaa
This change will add support for winbond "W25N02JWZEIF"
spi nand device.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I1dd258c3f0f3174d09e74fb7ffd0c26a43e6c24b
This change will add support for giga device GD5F1GQ5REYIG
spi nand support.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I57211ce34543de81216d86653a45519b97cf2fb0
This change will change serial training data read to one complete
page instead of 64-bytes read. Partial page read will cause some
data curroption issue if read request failed so read one complete page.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: Ibad101f096440e5dc10dfb4b3329a0aa6bddee7d
This change will fix proper clock source macro in set_clk_rate function.
Currently we are passing the wrong value to qpic_set_clk_rate for clock
source.
wrong:
qpic_set_clk_rate(IO_MACRO_CLK_200_MHZ, QPIC_IO_MACRO_CLK, NAND_QSPI_MSTR_CONFIG);
The last argument should be clock source not register base address.
correct:
qpic_set_clk_rate(IO_MACRO_CLK_200_MHZ, QPIC_IO_MACRO_CLK, GPLL0_CLK_SRC);
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: Ie9e07c253220924fd0c9287f7f0e2c5d42351128
This change will fix memory leak problem in serial training.
For serial tarining we are allocating memory to hold the training
pattern buf. For any failure we are freeing the buffer but due to
wrong lavel used memory was not getting freed due to this memory leak
problem is happening.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I35ffd27df9b24ea53aed9e9f0623d8890ba66f06
This change fix Access violation created by APPS
master by accessing QPIC_XPU issue due to accessing
QPIC_QSPI_MSTR_CONFIG & QPIC_NAND_FLASH_SPI_CFG registers
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ibb840db12359eea01823dd7732fcb1ac1e7b8967
This change will fix erase address configuration for QSPI
nand devices whose density is beyond 128MiB.
To erase a block as per datasheet of serial nand device
page row address <5:0> and the Block row address <16:6>.
In code we are forming directly pages address starting
from <16:0> i.e 17-bit address. Currently we are configuring
address_0 and address_1 register as follws.
addr0 = (page << 16) and addr1 = 0x0;
This logic will work if device size upto 128MiB, but if device
size beyond 128MiB then this logic will fail becasue upper most bit
will go out of add0 register.
Fixing this by changing address configuration logic for erase block.
addr0 = (page << 16) addr1 = (page >> 16) & 0xffff;
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I4950bb611780257629491ffbb42c91fcfedebc58
This change will define qspi_debug macro to print
debug messages.
Change-Id: I49c5278f63fa53dc5b2237aeb9bfef97990ecc86
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This change will enable config for serial training.
This change also fix the the logic to get most appropriate phase
out of passed phase.
This change also add support to read serial training offset from
partition table. Also patching freqency value & phase value to kernel.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: Ibb4a5cd80f16605e8e91bdf6a0c6c484edff1735
This change will fix NULL pointer dereference while reading
from spi nand flash in oobbuf.
The multipage read features is only to read with ecc for
raw read/write the the access is page wise due to mtd layer
will request only one page at a time. So don't increment oobbuf
for every page while reading if already bitflips are present in spi
nand flash. if so data abort will happen due to NULL pointer
dereference.
error:
NAND read: device 0 offset 0x4480000, size 0x1000
data abort
pc : [<4a9515ec>] lr : [<44000e18>]
reloc pc : [<4a9515ec>] lr : [<44000e18>]
sp : 4a77f6f4 ip : bbfff3dc fp : 4a783510
r10: 4a97bb40 r9 : 4a77feb0 r8 : 44000e0c
r7 : 4a97ca2c r6 : 0000000f r5 : 00000004 r4 : 00000003
r3 : ffffffff r2 : 000001f4 r1 : 000000ff r0 : 44000e0c
Flags: nzCv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
resetting ...
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I435f65183b56ceef64bad7d0df7ffebe02175a66
This change will fix serial training logic and enable
config to enable default qpic_io_macro clock @ 80MHz with
default phase delay valu 4 for all qspi serial line.
This change also fix the delay issue while writing to qpic
register via bam.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I345f736fdae9d48b6da0115ca7a8519b43fe9efd
This change will add support to write some ops group register via
BAM to avoid xPU error.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I65ea875f783b7254f01cb3cf43eb43295caa4ed9
This change will add support for serial training in
QPIC.
Due to different PNR and PCB delays, serial read data
can come with different delays to QPIC. At high frequency
operations Rx clock should be adjusted according to delays
so that Rx Data can be captured correctly. CLK_CNTR_INIT_VAL_VEC
in NAND_FLASH_SPI_CFG register is a 12-bit vector which is divided
in 4 parts of 3 bits each representing delay of 4 serial input data
lines. Bit [2:0] corresponds to qspi_miso[0], bit [5:3] corresponds
to qspi_miso[1], bit [8:6] corresponds to qspi_miso[2] and bit [11:9]
corresponds to qspi_miso[3]. Delay of each qspi_miso line can be set
from 0 to 7.
For serial training the following rule should be followd.
1) SW should write a page with any known pattern in flash at lower
frequency.
2) Set the CLK_CNTR_INIT_VAL_VEC for qspi_miso[0] line.
3) Read that page repetitively in high frequency mode until it
gets data accurately.
4) Repeat above steps for other qspi_miso lines.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: If622809efff55fb2abe60f409a590abd5313741b
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This change will enable page_scope_read & multipage_read support for
QPIC.
QPIC version 2.0 onwards , QPIC support page_scope_read &
multipage_read command to enhance the read performance.
In normal page read command SW is needed to write EXEC_CMD register
for each Code word and collect any Status related to that CW before
issueing EXEC_CMD for next CW.
For page_scope read command SW is required to issue EXEC_CMD
only once for a page. Controller HW takes care of Codeword specific
details and automatically returns status associated with each CW to
BAM pipe, dedicated for status deposition.
enabling all bits in NAND_AUTO_STATUS_EN will require 4 data
descriptors of 24 bytes each. This will publish all NANDc status
registers in system memory.
For multipage_read command SW is required to issue EXEC_CMD only
once for all the pages which configured in QPIC_NAND_MULTI_PAGE_CMD
register.
All interrupts will be operational and valid in these modes.
To check the status for each codeword, it is not possible to access
the status registers while the read command is operational in
page_scope & multi_page read modes. Hence, another feature to publish the
status data (for all NAND status registers) by programming the
NAND_AUTO_STATUS_EN register.
For serial NAND:
Read command for page_scope_read = 0x78800032 (QPIC_NAND_FLASH_CMD)
Read command for multi_page_read = 0x78400032 (QPIC_NAND_FLASH_CMD)
For Parallel NAND:
Read command for page_scope_read = 0x00800032 (QPIC_NAND_FLASH_CMD)
Read command for multi_page_read = 0x00400032 (QPIC_NAND_FLASH_CMD)
Now we fixed maximum data bytes read in one go 128KiB(2KiB page),
256KiB (4KiB page), 512 KiB (8kiB page), because from upper layer
we are getting more than 128KiB data bytes request in one go. if so
just changing the value of "MAX_MULTI_PAGE" macro will increase the
maximum data bytes in one go.
Change-Id: I48eea51ff8f5f79f3490d8a538c295ecc3eeee19
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Since nand configuration is fixed across all HK boards,
removing the nand gpio_entries from device tree and
adding static board param entries. This helps reduce
image footprint and opens up space for new board support.
Change-Id: I89bc11165a6cdfcdb3b4650a73cbeea17895f991
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
This change will add support for serial nand.
QPIC-2.1.1 supports parallel nand as well as serial nand.
QPIC will operate either in parallel configuration or
serial nand. Both can't work together.
This change will support initially four serial nand parts.
MT29F1G01ABBFDWB-IT (Micron-0x2C,0x15, 2K + 128)
GD5F1GQ4RE9IG (Giga Device-0xC8,0xC1, 2K + 128)
GD5F2GQ5REYIH (Giga Device-0xC8,0x22, 2K + 64)
GD5F1GQ4RE9IH (Giga Device-0xC8, 0xC9, 2K + 64)
Device Internal ECC is disabled for all three devices. This change will
enabele QPIC ECC engine.
For MT29F1G01ABBFDWB-IT 4-bit ECC as well 8-bit ECC will be supported.
For GD5F1GQ4RE9IG 4-bit ECC as well 8-bit ECC will be supported.
For GD5F2GQ5REYIH only 4-bit ECC will be supported due to 64-bytes spare.
For GD5F1GQ4RE9IH only 4-bit ECC will be supported due to 64-bytes spare.
Change-Id: I3f38f9c76b7bb235bb335a481fbc42ae1bd00395
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This patch fixes the nand flash size access issue
found in flash with two logical units
Change-Id: Ifcbaa40709c4ac5d508b629fcc6cf7006f167628
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
This change will read entire ONFI parameter page. This will helpful
while validating new ONFI AVL part.
To read entire ONFI parameter page data structure use command:
"#nand onfipara".
Change-Id: Icea80fce6900716871d8c82a2d1ac0c00531af98
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Currently, the nand driver expects the start address to be page
aligned. This patch adds the support for reading data from
non-page aligned start address by using intermediate buffer.
1. Determine the number of pages with start address and
length.
2. Do the full page read for all the pages. For first page,
check the start address and determine the column. If column is
non-zero then use the intermediate buffer for page data and copy
the required number of bytes from this intermediate buffer to
actual buffer.
Change-Id: I05a4b98547c83f785096027596cedd83a283edd8
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
