This change will add support for 4K Macronix spi nand
"MX35UF4GE4AD-Z4I"
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Change-Id: I94e07d9e25de46c67fcb679ef149990e093afc8f
This change will add support for Macronix "MX35UF1GE4AC" spi nand
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I66e82e22217d655b44e30baa64f3aefd5a5f2aaa
This change will add support for winbond "W25N02JWZEIF"
spi nand device.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I1dd258c3f0f3174d09e74fb7ffd0c26a43e6c24b
This change will add support for giga device GD5F1GQ5REYIG
spi nand support.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I57211ce34543de81216d86653a45519b97cf2fb0
This change will change serial training data read to one complete
page instead of 64-bytes read. Partial page read will cause some
data curroption issue if read request failed so read one complete page.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: Ibad101f096440e5dc10dfb4b3329a0aa6bddee7d
This change will fix proper clock source macro in set_clk_rate function.
Currently we are passing the wrong value to qpic_set_clk_rate for clock
source.
wrong:
qpic_set_clk_rate(IO_MACRO_CLK_200_MHZ, QPIC_IO_MACRO_CLK, NAND_QSPI_MSTR_CONFIG);
The last argument should be clock source not register base address.
correct:
qpic_set_clk_rate(IO_MACRO_CLK_200_MHZ, QPIC_IO_MACRO_CLK, GPLL0_CLK_SRC);
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: Ie9e07c253220924fd0c9287f7f0e2c5d42351128
After reading data from mmc, dest pointer will point to
the end address. To calculate the start of dest pointer
number of bytes copied has to be subtracted.
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Change-Id: I24610a3b3bb498c4ee4ebba58e557d109c6af1ef
This change will fix memory leak problem in serial training.
For serial tarining we are allocating memory to hold the training
pattern buf. For any failure we are freeing the buffer but due to
wrong lavel used memory was not getting freed due to this memory leak
problem is happening.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I35ffd27df9b24ea53aed9e9f0623d8890ba66f06
This change make the qca_8337 switch initialization generic based on
dts irrespective of gmac controller.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I292992307ead2cd7bbb0763ff483dc16c266d417
This change fix Access violation created by APPS
master by accessing QPIC_XPU issue due to accessing
QPIC_QSPI_MSTR_CONFIG & QPIC_NAND_FLASH_SPI_CFG registers
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ibb840db12359eea01823dd7732fcb1ac1e7b8967
This change will fix erase address configuration for QSPI
nand devices whose density is beyond 128MiB.
To erase a block as per datasheet of serial nand device
page row address <5:0> and the Block row address <16:6>.
In code we are forming directly pages address starting
from <16:0> i.e 17-bit address. Currently we are configuring
address_0 and address_1 register as follws.
addr0 = (page << 16) and addr1 = 0x0;
This logic will work if device size upto 128MiB, but if device
size beyond 128MiB then this logic will fail becasue upper most bit
will go out of add0 register.
Fixing this by changing address configuration logic for erase block.
addr0 = (page << 16) addr1 = (page >> 16) & 0xffff;
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I4950bb611780257629491ffbb42c91fcfedebc58
This changes add CONFIG_CMD_NAND flags in flash command and smem
source file to eliminate nand specific source if CONFIG_CMD_NAND
is not defined.
This changes replace CONFIG_IPQ_MTD_NOR with CONFIG_MTD_DEVICE flag
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I612ae89c3730dc86f2693088fb4cb5c10763165d
This changes add 8033 phy support in MP02.1(Ap & Db) RDP
in tiny nor flash
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ib35faba4321c70fed007c923ff0f5e618fad0276
This changes remove the phy_name from all mpXX dts and
handle by driver itself.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ia2d0379151db0c68a0b28f5062e83f80579d37c1
This changes removes NAPA support from tiny U-boot config
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I057064d63a3ac0788275a4572242cc251a445a98
This change will define qspi_debug macro to print
debug messages.
Change-Id: I49c5278f63fa53dc5b2237aeb9bfef97990ecc86
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This change will enable config for serial training.
This change also fix the the logic to get most appropriate phase
out of passed phase.
This change also add support to read serial training offset from
partition table. Also patching freqency value & phase value to kernel.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: Ibb4a5cd80f16605e8e91bdf6a0c6c484edff1735
This change will fix NULL pointer dereference while reading
from spi nand flash in oobbuf.
The multipage read features is only to read with ecc for
raw read/write the the access is page wise due to mtd layer
will request only one page at a time. So don't increment oobbuf
for every page while reading if already bitflips are present in spi
nand flash. if so data abort will happen due to NULL pointer
dereference.
error:
NAND read: device 0 offset 0x4480000, size 0x1000
data abort
pc : [<4a9515ec>] lr : [<44000e18>]
reloc pc : [<4a9515ec>] lr : [<44000e18>]
sp : 4a77f6f4 ip : bbfff3dc fp : 4a783510
r10: 4a97bb40 r9 : 4a77feb0 r8 : 44000e0c
r7 : 4a97ca2c r6 : 0000000f r5 : 00000004 r4 : 00000003
r3 : ffffffff r2 : 000001f4 r1 : 000000ff r0 : 44000e0c
Flags: nzCv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
resetting ...
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I435f65183b56ceef64bad7d0df7ffebe02175a66
This change will fix serial training logic and enable
config to enable default qpic_io_macro clock @ 80MHz with
default phase delay valu 4 for all qspi serial line.
This change also fix the delay issue while writing to qpic
register via bam.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I345f736fdae9d48b6da0115ca7a8519b43fe9efd
This Gephy is internal phy driver for ethernet
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ia4e744c0fbd990bdc94fe93263ac2ddbe4cecf61
This change will add support to write some ops group register via
BAM to avoid xPU error.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I65ea875f783b7254f01cb3cf43eb43295caa4ed9
This changes initialize clock and enable the block of
Gephy, Uniphy, GMAC0 & GMAC1 and also udpate Rx & Tx clock
based on speed.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ia2627e17f7029c2d0d1cbb9eff26afb27aa1c057
This change will add support for serial training in
QPIC.
Due to different PNR and PCB delays, serial read data
can come with different delays to QPIC. At high frequency
operations Rx clock should be adjusted according to delays
so that Rx Data can be captured correctly. CLK_CNTR_INIT_VAL_VEC
in NAND_FLASH_SPI_CFG register is a 12-bit vector which is divided
in 4 parts of 3 bits each representing delay of 4 serial input data
lines. Bit [2:0] corresponds to qspi_miso[0], bit [5:3] corresponds
to qspi_miso[1], bit [8:6] corresponds to qspi_miso[2] and bit [11:9]
corresponds to qspi_miso[3]. Delay of each qspi_miso line can be set
from 0 to 7.
For serial training the following rule should be followd.
1) SW should write a page with any known pattern in flash at lower
frequency.
2) Set the CLK_CNTR_INIT_VAL_VEC for qspi_miso[0] line.
3) Read that page repetitively in high frequency mode until it
gets data accurately.
4) Repeat above steps for other qspi_miso lines.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: If622809efff55fb2abe60f409a590abd5313741b
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
