This change will add support for serial training in
QPIC.
Due to different PNR and PCB delays, serial read data
can come with different delays to QPIC. At high frequency
operations Rx clock should be adjusted according to delays
so that Rx Data can be captured correctly. CLK_CNTR_INIT_VAL_VEC
in NAND_FLASH_SPI_CFG register is a 12-bit vector which is divided
in 4 parts of 3 bits each representing delay of 4 serial input data
lines. Bit [2:0] corresponds to qspi_miso[0], bit [5:3] corresponds
to qspi_miso[1], bit [8:6] corresponds to qspi_miso[2] and bit [11:9]
corresponds to qspi_miso[3]. Delay of each qspi_miso line can be set
from 0 to 7.
For serial training the following rule should be followd.
1) SW should write a page with any known pattern in flash at lower
frequency.
2) Set the CLK_CNTR_INIT_VAL_VEC for qspi_miso[0] line.
3) Read that page repetitively in high frequency mode until it
gets data accurately.
4) Repeat above steps for other qspi_miso lines.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: If622809efff55fb2abe60f409a590abd5313741b
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
a99d538e1b