This change will fix NULL pointer dereference while reading
from spi nand flash in oobbuf.
The multipage read features is only to read with ecc for
raw read/write the the access is page wise due to mtd layer
will request only one page at a time. So don't increment oobbuf
for every page while reading if already bitflips are present in spi
nand flash. if so data abort will happen due to NULL pointer
dereference.
error:
NAND read: device 0 offset 0x4480000, size 0x1000
data abort
pc : [<4a9515ec>] lr : [<44000e18>]
reloc pc : [<4a9515ec>] lr : [<44000e18>]
sp : 4a77f6f4 ip : bbfff3dc fp : 4a783510
r10: 4a97bb40 r9 : 4a77feb0 r8 : 44000e0c
r7 : 4a97ca2c r6 : 0000000f r5 : 00000004 r4 : 00000003
r3 : ffffffff r2 : 000001f4 r1 : 000000ff r0 : 44000e0c
Flags: nzCv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
resetting ...
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I435f65183b56ceef64bad7d0df7ffebe02175a66
This patch will tune ssuniphy to fixed
offset instead of SSC.
Signed-off-by: Manikanta Mylavarapu <mmanikan@codeaurora.org>
Change-Id: Ieca1e079275092ea49fcc1ffa9ba1dadadd2a93a
This patch will update usb3 configurtaion
based on ssphy availability.
Since usb3 ssphy shared with pcie phy,
certain configuration need to be done based
on ssphy availability.
Signed-off-by: Manikanta Mylavarapu <mmanikan@codeaurora.org>
Change-Id: I474a6ea269e7778738ca9464dae510bb58e8bcea
This changes fixup the mtdparts without support of
MTD framework,This code read the partition details from env
variable and patch to kernel dts.
Change-Id: I829808620c35b57973dc0ae015131bc5019c4844
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
This changes enable nor enviornemnt support if its no flash with
eMMC and NAND is disabled.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I1ff389ed388fb7f72543cc87e852c360a965db48
This changes update the TLV offset as per the kernel tlv crash region.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I27d79d5f2d35c4b584292410ee76d26b123d301f
We had identical device-tree for different RDPs
though they are the same except for machid.
This change enables reuse of a single device-tree
across RDPs with same configurations.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Change-Id: If81b431e4a6afe54e427fe0a52de275fdd29df00
This change fixes setting dirty bit in CMD_RCGR and configure GMAC
to run on GPLL4 clock source.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I01bb0e3af2da93f0464d41a6bd571480b1a4e581
Update usb controller and phy
configuration for enumeration.
Signed-off-by: Manikanta Mylavarapu <mmanikan@codeaurora.org>
Change-Id: I9e20fe5bf4c7abe7547f383ab58bff9b8dad64e0
This change will modify PULL value for eMMC CMD line.
with this change the pull value will be GPIO_PULL_UP.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: Id884ef4742dca5f2f30c699aa2ab48c0d3c7cc97
This change will fix serial training logic and enable
config to enable default qpic_io_macro clock @ 80MHz with
default phase delay valu 4 for all qspi serial line.
This change also fix the delay issue while writing to qpic
register via bam.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I345f736fdae9d48b6da0115ca7a8519b43fe9efd
This Gephy is internal phy driver for ethernet
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ia4e744c0fbd990bdc94fe93263ac2ddbe4cecf61
This changes remove emulation dts and add mp02.1 dts support in
Makefile for tiny-nor build
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I99d28415442b4079d4e67e586b794b88aba403a2
Remove support for hk05 since it is
marked as obsolete in default setting table
Signed-off-by: Karthick Shanmugham <kartshan@codeaurora.org>
Change-Id: I972af09f912c1f613b462cf2559d8a645a0bb270
This is missing, with causes lldiv() to fail on boards with use the private
libgcc. Add the missing routine.
Code is available for using the CLZ instruction but it is not enabled at
present.
This comes from coreboot version 4.0.
Signed-off-by: Simon Glass <sjg@chromium.org>
(cherry picked from commit 9ab60493c9)
Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org>
Change-Id: Id1d604819be2a98e1cc1ea306902a86323135679
This config need not be defined for IPQ806x. U-boot in
IPQ806x, can run without this CP15BEN setting.
Change-Id: I1b95e2a06f72dcc763a885f81b591d7d529dd446
Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org>
This change will remove GCC_SDCC1_MISC register from
SDCC clock configuration code path. Since in ipq5018 this
register is not available. so removining this register.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I980fc0f0ce24cd0da5610300608a5dd223c33941
This change will add support to write some ops group register via
BAM to avoid xPU error.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I65ea875f783b7254f01cb3cf43eb43295caa4ed9
This changes remove double calculation of N and D values.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I1c8444b5f6dbbc06a2b676477599978d6a91a681
