Currently, the nand driver expects the start address to be page
aligned. This patch adds the support for reading data from
non-page aligned start address by using intermediate buffer.
1. Determine the number of pages with start address and
length.
2. Do the full page read for all the pages. For first page,
check the start address and determine the column. If column is
non-zero then use the intermediate buffer for page data and copy
the required number of bytes from this intermediate buffer to
actual buffer.
Change-Id: I05a4b98547c83f785096027596cedd83a283edd8
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Currently NAND_CTRL register write generates error.
Register writes to operational registers should always be done
through command descriptors if BAM_MODE is already enabled.
For NAND boot, bootloader already enables BAM_MODE so read the
NAND_CTRL register value and write only if BAM_MODE is not set.
Change-Id: Iabc3e06dc7d8d8b36cdf35907217e1c4d7cc960a
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
If nand id table has specified oobsize then use the same.
Change-Id: I58b19f8f9989c7332d103b83b6920d5b59b29a13
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Following error is coming during UBI mount for non ONFI nand
device since mtd->writebufsize is coming as zero
ubi0: attaching mtd2
UBI init error 22
The mtd->writebufsize is being assigned currently for ONFI
devices only so move this assigment to common place.
Change-Id: Idd22800dd65035952c1afd07ba375a28ffcf76ad
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
The ONFI NAND device specifies the required ECC correction in its
param page but for non ONFI device, we don't have such info.
The QPIC NAND contoller can use 8 bit ECC if the chip has required
number of spare bytes. This patch calculates the minimum required
spare bytes for using 8 bit ECC and select the same, if non ONFI
device has required number of spare bytes otherwise 4 bit ECC
will be used.
Change-Id: If7c718f4288eee16857171335897e3209a05fd0b
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Add the full description of the Toshiba TH58NYG3S0H NAND chip
in the nand_ids table since its spare bytes are coming as 128
instead of 256 with standard calculation. This device is non
ONFI/JEDEC device.
Change-Id: If1938fbcd0ebceb70aa9b620186cc92c6d504f75
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Software SPI reset mode can be trigger from 4-Byte Address mode
in flash W25Q256JW.
Change-Id: I3f8ec46c2732c07a7af0cc7331102334413067ba
Signed-off-by: Santan Kumar <santank@codeaurora.org>
Do generic flash structure initialization, for the devices
not listed in the SPI NOR flash lookup table, so that
we can access the flash even before the support is added.
Block size and density are obtained from smem.
Change-Id: I568eb538615bb36124c43a2509bcfce2e4a1188a
Signed-off-by: Balaji Jagadeesan <bjagadee@codeaurora.org>
When 4K sector size support is enabled for spi, always
4K sector erase command is passed for all the erase operations.
To increase the performance, 64K erase command is
passed to the command buffer based on length and offset.
Change-Id: Ia762d192ba5d424f0ba3538fff8aff4954050bf7
Signed-off-by: Balaji Jagadeesan <bjagadee@codeaurora.org>
This patch adds the support on nand driver to work
when dcache is on.
flush_dcache_range will do both clean and invalidate.
To avoid any data loss when an un-aligned buffer used
in RX path, before giving buffer to bam and after bam
updates the data in buffer, buffer will be flushed.
Change-Id: Ib38d68726efe1692ae94c2be1af61cf29d1c2e50
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Some of the newer nand parts can have bit flips in an erased
page due to the process technology used. In this case, ipq
nand controller is not able to identify that page as an erased
page. In case of bitflips, the ECC engine tries to correct the
data and then it generates the uncorrectable error. Now, this
data is not equal to original raw data.
Following logic is being added to identify the erased
codeword bitflips.
1. Maintain the bitmasks for the codewords which generated
uncorrectable error.
2. Read the raw data again in temp buffer and count the
number of zeros. Since spare bytes are unused in ECC layout and
won’t affect ECC correctability so no need to count number of
zero in spare bytes.
3. If the number of zero is below ECC correctability then it
can be treated as erased CW. In this case, make all the data/oob
of actual user buffers as 0xff.
Change-Id: I5a80cd371a926efa36c40b4db68e78ed78c30536
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Following are the major issues in current implementation
1. The mtd layer expects the driver to return non-negative
integer representing the maximum number of bitflips that were
corrected on any one ecc region. The mtd layer takes care of
returning EUCLEAN based on returned number.
2. The read should return the complete data in case of
EBADMSG so move the EBADMSG check in the main read function.
Change-Id: Iab3a28427e8350e8c99368762373f2cbce918786
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
1. assign ecc strength in mtd structure which will be used by
mtd layer
2. Initialize bitflip_threshold with 3*4 of ecc strength so
that MTD layer will return EUCLEAN if number of ecc correction
are more than bitflip_threshold.
Change-Id: I81cfe6059375117ced7888b877705919287a7be2
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
This is a snapshot of the spi_nand as of uboot-1.0
commit:
e6434d80905a219860c8ede78377221ded2510f2 (ipq40xx:
Add bit-flip threshold for QPIC NAND)
Change-Id: I91db5822cc450e9d7eb52fca9eab213784547206
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
1. This driver is directly being registered with MTD
layer.So for OOB operations, the device OOB size will be
passed. NAND controller can’t handle the complete OOB so
calculate NAND Controller supported OOB size and overwrite
the device OOB size with that.
2. Enabling 8 bit ECC support in dev0_ecc_cfg register
Change-Id: I5f4297932eea6bed47182d235d081cbe30d1b85c
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Some of the newer nand parts can have bit flips in an erased
page due to the process technology used. In this case, qpic
nand controller is not able to identify that page as an erased
page. In case of bitflips, the ECC engine tries to correct the
data and then it generates the uncorrectable error. Now, this
data is not equal to original raw data.
Following logic is being added to identify the erased
codeword bitflips.
1. Maintain the bitmasks for the codewords which generated
uncorrectable error.
2. Read the raw data again in temp buffer and count the
number of zeros. Since spare bytes are unused in ECC layout and
won’t affect ECC correctability so no need to count number of
zero in spare bytes.
3. If the number of zero is below ECC correctability then it
can be treated as erased CW. In this case, make all the data/oob
of actual user buffers as 0xff.
Change-Id: Ie0427c6802e2e41234137e0fbbf51c5a50a35946
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
This patch does minor code reorganization to store spare, ecc and
bbm bytes in nand device structure which will be useful in
subsequent patches.
Change-Id: Id44c53e204a874569968764798c346a609695acf
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Following are the major issues in current implementation for
checking the read errors
1. For checking the erased CW, NAND_ERASED_CW_DETECT_STATUS
is being read inside qpic_nand_check_status. The
qpic_nand_check_status will be called after complete page read
so reading status register won’t help in getting the register
value after each CW reads.
2. The mtd layer expects the driver to return non-negative
integer representing the maximum number of bitflips that were
corrected on any one ecc region. The mtd layer takes care of
returning EUCLEAN based on returned number.
3. mtd->ecc_stats is only applicable when ECC engine is
doing ECC correction. For raw reads, the stats should not be
incremented.
Now the changes have been done to reorganize the error handling
1. schedule the NAND_ERASED_CW_DETECT_STATUS reading after
every CW read and check the same if ECC engine generates
uncorrectable error.
2. For raw read, the ECC engine will never generate the
uncorrectable error or erased CW so check only
NAND_FLASH_STATUS.
3. The qpic_nand_read_oob should return the maximum number
of bitflips that were corrected on any one ecc region so
introduce the max_bitflips for maintaining the same.
4. The read should return the complete data in case of
BADMSG so move the BADMSG check in the main read function.
Change-Id: Ibef56294ace00d7cd67b501f623fb1d3aeb2c6ec
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
1. ecc strength can be assigned in mtd structure itself so
remove the ecc_width from qpic nand dev structure
2. Initialize bitflip_threshold with 3*4 of ecc strength so
that MTD layer will return EUCLEAN if number of ecc correction
are more than bitflip_threshold.
Change-Id: Ieafd1957b89a05f9dd0fdfe829712d8891bd6a48
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
NANDC_RESULT_BAD_PAGE is not being returned by any operation, so
it can be removed.
Change-Id: Ia90e4e6b7ef7577d069d312d51083b50f49bf980
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Reset command must be the first command issued to all
targets after the NAND flash device is powered on.
Change-Id: I617dc5b0ad8d72705dcf20f1cb554134b166e533
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
The UBI layer generates the following data aborts if any of the
NAND block contains bit flips
ubi0: attaching mtd2
ubi0: fixable bit-flip detected at PEB 149
ubi0: scanning is finished
ubi0: fixable bit-flip detected at PEB 149
data abort
pc : [<4a934cc8>] lr : [<4a933aec>]
reloc pc : [<4a934cc8>] lr : [<4a933aec>]
sp : 4a77f2e0 ip : 00000095 fp : 00000075
r10: 000001b7 r9 : 4a77fea0 r8 : 00000001
r7 : 0001f000 r6 : 0001f000 r5 : 4a785e40 r4 : 4a7c4180
r3 : 00000000 r2 : 00000075 r1 : 4a7860b8 r0 : 4a7c49c0
Flags: nzcv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
UBI layer will move the data from original block to some other
block in case of bit flips in the function ubi_eba_copy_leb. This
function uses volume EBA table vol->eba_tbl. The current UBI code
calls ubi_wl_init followed by ubi_eba_init but the ubi_eba_init
only initializes the volume EBA table. In case of bit failure,
the ubi_wl_init calls function __schedule_ubi_work which will
call ubi_eba_copy_leb and triggers data abort.
ubi_attach() {
ubi_wl_init -> __schedule_ubi_work -> ubi_eba_copy_leb
ubi_eba_init
}
The UBI code has been written for Linux kernel and it has been
ported to UBOOT. Since UBOOT does not support threads so all the
thread functions are being called in uboot synchronously.
In Linux kernel, the UBI background thread starts
after the initialization, which is being controlled by
thread_enabled variable which will be set to true after all
initialization.
Now this patch checks for thread_enabled variable and call the
do_work only if the thread is enabled.
Change-Id: I4b2b40031dbd5f16ceefef541248973ca326cd9c
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
NAND_CMD_PRG_PAGE_ALL uses the spare data from buffer itself
which is not applicable. The spare area in NAND page for
QPIC are dummy bytes so 0xff should be written to these
spare area. NAND_CMD_PRG_PAGE does the same thing and HLOS
driver uses this command for all page program
operations. The actual spare data is being written along
with every codeword since the codewords size is 516 in which
512 bytes are user data and 4 bytes are spare data.
Change-Id: I5651caf5ea95f046570e8318f59e140398869ece
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
1. This driver is directly being registered with MTD
layer so for OOB operations, the device OOB size will be
passed. QPIC can’t handle the complete OOB so calculate QPIC
supported OOB size and overwrite the device OOB size with
QPIC supported OOB size.
2. OOB available calculation was wrong. The available OOB’s are
4 bytes per codeword.
3. Raw configuration codeword size was hardcoded to 528 while 8
bit ECC codeword size is 532.
Change-Id: Idc118e2fdd9882758da9dc6b1e977e04697a5640
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
The QPIC XFER STEPS will not be configured in non NAND boot
mode and the data transfer speed will be very slow. Now this
patch reads the timing parameter from ONFI page and configures
the NAND XFER STEPS registers for highest supported ONFI mode.
For NON ONFI device, it will configure to default mode.
Change-Id: I2daf4a92255307efc53db9bb7fe2f02e8c00c3fa
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
As the U-boot source is going to be common between ARM and MIPS
architecture , it is required to pick only the files specific
to the respective architectures during the build.
So, move the qca arm target specific common files to another
sub level by specifying the ARCH arm.
Change-Id: I06b538834109981f21fef6270bfb8e437a2f5a7e
Signed-off-by: Prabhu Jayakumar <pjayak@codeaurora.org>
The writebufsize is introduced in mtd struct for the ubi fastmap
support.
This is not initialized in the qpic nand driver which leads to ubi
error.
Fixed the following ubi error.
bad write buffer size 0 for 2048 min. I/O unit
UBI init error 22
Change-Id: I35778366b95930bd01108bf300f073ee21940bc6
Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
