The DSA port code is trying to flush associated VLANs whenever the MST
state is changed. This functionality is available on a per port+vid based
using the L2_TBL_FLUSH_CTRL which is already used for the .port_fast_age
callbacks.
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The realtek DSA switch driver sets up all VLANs using CIST. It is therefore
not necessary to enforce CIST using the ST_CTRL register.
This allows us later to overwrite the MSTI of VLANs. This is necessary to
get MSTP working on RTL93xx.
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This pull request is based on
- the discussions in https://forum.openwrt.org/t/adding-openwrt-support-for-linksys-mr6350
- https://github.com/openwrt/openwrt/pull/11405 which added support for similar devices.
Device Specs:
- IPQ4019
- Quad Core CPU
- 256 MB RAM
- 256 MB FLASH
- 4 LAN ports, 1 WAN port
- 2.4GHz (802.11n) and 5GHz (802.11c) wifi
- 3 LEDs (Red, blue, green) which are routed to one indicator at the top of the case
- 2 buttons (Reset, WPS)
Disassembling the device:
- There are 4 screws at the bottom of the device which must be removed
- Two are under the fron rubber feets
- Two are under the labels in the back (corner next to the rear rubber feets)
Serial interface:
- The serial interface is already populated on the device with a 6-pin header
- Pin 1 is next to the heatsink
- Pinout: 1: 3.3V, 2: TX, 3: RX, 4: unknown, 5: GND, 6: GND
- Settings: 115200, 8N1
Migrating to OpenWrt requires multiple steps:
- Load and boot the initramfs image
- Adapt U-Boot settings to support bigger kernels
- Flash the sysupgrade image
Load and boot initramfs:
- Connect serial interface
- Set up a TFTP server on IP 192.168.1.254
- Copy openwrt-ipq40xx-generic-linksys_mr6350-initramfs-zImage.itb to TFTP server
- Rename file to C0A80101.img
- Boot up the device and stop in U-Boot
- Run the following U-Boot commands after a link has been established:
tftp
bootm
- Initramfs image is started now.
Adapt U-Boot settings to support bigger kernels:
- Run "fw_printenv" in the initramfs image after booting
- There should be an entry kernsize=300000 which indicates the maximum size for the kernel is 3MB
- Execute "fw_setenv kernsize 500000" to increase the max kernel size to 5MB
- Check that the change are applied with "fw_printenv"
Flash the sysupgrade image:
- Default sysupgrade routine either with a initramfs image containing LuCI or via command line.
Revert back to OEM firmware:
- Only tested with FW_MR6350_1.1.3.210129_prod.img
- Flash the OEM firmware via sysupgrade
- Forced update is required
Signed-off-by: Roland Reinl <reinlroland+github@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17977
Signed-off-by: Robert Marko <robimarko@gmail.com>
This device has only half the flash and ram of the RBR20. It also has
two lan ports instead of wan and lan.
Hardware
--------
SOC: Qualcomm IPQ4019
FLASH: 128MB (Winbond W29N01HVSINF)
RAM: 256MB (Winbond W632GU6MB-12)
WIFI: Qualcomm IPQ4019
Qualcomm Atheros QCA9886
ETH: 2x LAN
LED: 5 (4 RGB at top, 1 RG at back)
BTN: WPS, Reset
UART: 115200 8N1 (dotted Pin = VCC) VCC-TX-RX-GND
MAC addresses
-------------
LAN Label MAC (stored in boarddata1 offset 0x0)
2.4G LAN
5GLow LAN + 3 (stored in boarddata1 offset 0xc)
5GUpper LAN + 2 (stored in boarddata1 offset 0x12)
Installation
------------
Either use the vendor ui upgrade method or nmrpflash to install the
factory image.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20560
Signed-off-by: Robert Marko <robimarko@gmail.com>
This device shares a lot of similarities with the LBR20 - the RBR20 just
misses the LTE modem and its formfactor is alot smaller. Other than that
the LED configuration matches other RBR devices but the RBR20 has less
LEDs than its larger counterparts.
Hardware
--------
SOC: Qualcomm IPQ4019
FLASH: 256MB (Winbond W29N02GVSIAF)
RAM: 512MB (Nanya NT5CC256M16EP-EK)
WIFI: Qualcomm IPQ4019
Qualcomm Atheros QCA9886
ETH: 1x WAN, 1x LAN
LED: 5 (4 RGB at top, 1 RG at back)
BTN: WPS, Reset
UART: 115200 8N1 (dotted Pin = VCC) VCC-TX-RX-GND
MAC addresses
-------------
LAN Label MAC (stored in boarddata1 offset 0x0)
WAN LAN + 1 (stored in boarddata1 offset 0x6)
2.4G LAN
5GLow LAN + 3 (stored in boarddata1 offset 0xc)
5GUpper LAN + 2 (stored in boarddata1 offset 0x12)
Installation
------------
Either use the vendor ui upgrade method or nmrpflash to install the
factory image.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20560
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL838x+RTL839x both configure a default QoS behavior with a default
mapping. This also needs to be added to RTL93xx to ensure a consistent
behavior:
* Set the default mapping between DSCP and priority: prio = dscp >> 3.
* Set the default mapping between internal priority and queues
* Set uniform prioritization of queues (as with other SoCs)
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20640
Signed-off-by: Robert Marko <robimarko@gmail.com>
If link aggregation with LACP is activated, we must send out the LACP
packets on the physical port and not on a logic port. Otherwise, the per
port packets might be (rebalanced) between the different ports in a link
aggregation group.
Such rebalancing breaks 802.3ad and will leave ports in a churned state.
Fixes: 8c42e63a69 ("realtek: rtl93xx: fix incorrect destination port selection")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20728
Signed-off-by: Robert Marko <robimarko@gmail.com>
If ports of a RTL93xx switch are not added to a port matrix then they are
not used for the link aggregation. As result, communication will then just
break on non-primary interfaces.
This can be reproduced in balanced-xor and 802.3ad bandwidth mode.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20729
Signed-off-by: Robert Marko <robimarko@gmail.com>
Commit 56e9a73d0b added support for configuring the SerDes polarity for
both RTL930X and RTL931X. Based on the code in the Realtek SDK in [1]
and [2], in both cases the same register bits are set. Thus, a common
implementation was provided which worked with e.g. USXGMII or 10GBase-R
configured SerDes.
However, after further tests, a strange issue occured where it didn't
work that well for all SerDes configurations. While running fine for
10GBase-R links on two adjacent SerDes, it didn't for 1000Base-X links
on one of two adjacent SerDes with the link not being detected as a
symptom.
Diving into the SDK again revealed that the referenced implementation of
polarity configuration is (by accident or by purpose) misleading. While
[1] and [3] for RTL930X match, [2] and [4] for RTL931X actually don't.
[4] writes the bits for the 1G polarity setting on different background
SerDes, thus in another frontend page.
Split implementations for RTL930X and RTL931X again and adjust the one
for RTL931X according to [4]. This resolves the issues with 1000Base-X
behavior.
[1] 69d2890a2e/sources/rtk-xgs1210/src/hal/phy/phy_rtl9300.c (L1384)
[2] 69d2890a2e/sources/rtk-xgs1210/src/hal/phy/phy_rtl9310.c (L3479)
[3] 69d2890a2e/sources/rtk-xgs1210/src/dal/longan/dal_longan_construct.c (L2246)
[4] 69d2890a2e/sources/rtk-xgs1210/src/dal/mango/dal_mango_construct.c (L1550)
Fixes: 56e9a73d0b ("realtek: pcs: rtl93xx: provide proper SerDes polarity
configuration")
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20767
Signed-off-by: Robert Marko <robimarko@gmail.com>
The MikroTik RouterBOARD 962UiGS-5HacT2HnT (hAP ac) currently comes up
with random MAC addresses. Assign the MAC addresses from hard_config for
LAN and WAN ports.
Fixes: c2140e32ce ("ath79: add support for MikroTik RouterBOARD 962UiGS-5HacT2HnT (hAP ac)")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://github.com/openwrt/openwrt/pull/20782
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add mt7987-2p5g-phy-firmware to DEVICES_PACKAGES of the MT7987A RFB as
well as the BananaPi R4 Lite.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Use skb->encapsulation flag instead of skb_tnl_header_len() to detect
encapsulated packets. Prevents false positives on non-encapsulated packets.
Reported-by: Mason-cw Chang (張哲維) <Mason-cw.Chang@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Usage of strlcpy results in a compilation error. strscpy is preferred
anyways and equivalent for our case.
Signed-off-by: David Bauer <mail@david-bauer.net>
This is an automatically generated commit which aids following Kernel patch
history, as git will see the move and copy as a rename thus defeating the
purpose.
For the original discussion see:
https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
This is an automatically generated commit.
When doing `git bisect`, consider `git bisect --skip`.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
CMCC PZ-L8 is a 2.4/5 GHz band 11ax (Wi-Fi 6) router, based on IPQ5000.
Specifications:
- SoC : Qualcomm IPQ5000
- RAM : Integrated 256MiB DDR3L
- Flash : 128 MiB SPI-NAND (ESMT F50D1G41LB)
- WLAN : 2.4/5 GHz 2T2R
- 2.4 GHz : Qualcomm IPQ5000 (SoC)
- 5 GHz : Qualcomm Atheros QCN6102
- Ethernet : 4x 10/100/1000 Mbps
- switch : Qualcomm Atheros QCA8337
- LEDs/Keys (GPIO) : 2x LEDs, 2x Keys
- UART : Through-hole on PCB, 4pins in the middle of the black aluminum heat sink
- assignment : 3.3V, GND,TX, RX (from left to right)
- settings : 115200n8
- Power : 12 VDC, 1 A
Flashing Instructions:
1. SSH Method
(1) Enable SSH on the stock firmware
a. Version 501.8 and 501.9:
Log in to http://192.168.10.1 with the password on the sticker
Append "/admin/system/admin" to the URL and press Enter
Delete "Dropbear instance", click "Add instance", then "Save and Apply"
Reboot the router
b. Version 501.11 and 501.12:
While the router is running the stock firmware, press and hold the reset button for 20-30 seconds
Open http://192.168.10.1:56781 and login with username "root" and the password on the sticker
Run "vi /etc/config/dropbear" and delete the line "option enable '0'"
Reboot the router
(2) Upload the factory.ubi file to router's /tmp directory (using scp or wget)
and execute the following commands in the router's shell
export rootfs=$(cat /proc/mtd | grep rootfs | grep -v _ | cut -d: -f1)
ubidetach -f -p /dev/${rootfs}
ubiformat /dev/${rootfs} -y -f /tmp/factory.ubi
2. U-Boot Method using UBI Image
Place the factory.ubi file on your TFTP server, enter U-Boot CLI and exec these commands
tftpboot <your_tftp_server_ip>:factory.ubi
flash rootfs
reset
3. U-Boot Method using initramfs Image
(1) Place the openwrt-*-initramfs-fit-uImage.itb file on your TFTP server
and rename it to initramfs.bin
(2) Enable serial console, enter to U-Boot CLI and exec these commands
tftpboot <your_tftp_server_ip>:initramfs.bin
bootm
(3) Once boot completed, upload the sysupgrade.bin file to router's /tmp directory
(using scp or wget) and execute the following command in openwrt shell
sysupgrade -n /tmp/sysupgrade.bin
Switching to the Stock Firmware:
Please follow the commit 3b7d72bc2e
Partition Layout (Stock Firmware):
0x000000000000-0x000000080000 : "0:SBL1"
0x000000080000-0x000000100000 : "0:MIBIB"
0x000000100000-0x000000140000 : "0:BOOTCONFIG"
0x000000140000-0x000000180000 : "0:BOOTCONFIG1"
0x000000180000-0x000000280000 : "0:QSEE"
0x000000280000-0x000000380000 : "0:QSEE_1"
0x000000380000-0x0000003c0000 : "0:DEVCFG"
0x0000003c0000-0x000000400000 : "0:DEVCFG_1"
0x000000400000-0x000000440000 : "0:CDT"
0x000000440000-0x000000480000 : "0:CDT_1"
0x000000480000-0x000000500000 : "0:APPSBLENV"
0x000000500000-0x000000640000 : "0:APPSBL"
0x000000640000-0x000000780000 : "0:APPSBL_1"
0x000000780000-0x000000880000 : "0:ART"
0x000000880000-0x000000900000 : "0:TRAINING"
0x000000900000-0x000004300000 : "rootfs"
0x000004300000-0x000007d00000 : "rootfs_1"
Notes:
This device is almost the same as ELECOM WRC-X3000GS2, including partition layout and the dual-boot feature.
Known Issues:
- All Wi-Fi related peripherals are disabled in device tree, since 256 MiB RAM is too few for ath11k.
- This device has another version with nand flash FM25SL01, which is not supported at the moment.
https://github.com/immortalwrt/immortalwrt/blob/master/target/linux/mediatek/patches-6.12/342-mtd-spinand-Support-fmsh.patch
MAC Addresses:
Interface MAC Address Location (binary)
LAN A4:39:B6:xx:xx:9D (0:ART, 0x00-0x05)
WAN A4:39:B6:xx:xx:9E (0:ART, 0x06-0x0B)
2.4 GHz A4:39:B6:xx:xx:9F (0:ART, 0x0C-0x11)
5 GHz A4:39:B6:xx:xx:A0 (0:ART, 0x12-0x17)
Signed-off-by: Chang Liu <jssqliuchang@gmail.com>
The "old" QCA8084 PHY driver does not implement 10g-qxgmii support.
This is blocking several devices which use the QCA8084 form being
merged. Qualcomm has provided updated drivers for the MAC (ppe), PCS,
and PHY via github. We only need to update the PHY driver.
Update the QCA8084 PHY driver using the patches provided by Qualcomm.
Re-organize the patches so that the changes go into the existing
patches. The SERDES functionality is new, so it gets new patches. This
is sufficient to enable 10g-qxgmii on ipq95xx platforms.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20721
Signed-off-by: Robert Marko <robimarko@gmail.com>
Replace Airoha AN7583 pinctrl patch with upstream version as it has been
accepted upstream. Add the related kernel version tag to identify it.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The unit-address of the ubi partition was @a9c0000 but the partition
actually starts at offset 0x0ad00000. Ideally they should match, so
align them.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20733
Signed-off-by: Robert Marko <robimarko@gmail.com>
The name "is_lagmember" implies that the port is part of a LAG. But this
information is already stored in lagmembers. In reality, it is stored the
non-primary LAG members. Renaming it accordingly, makes the code a lot more
readable
Also the type (u32 array) looks like it would contain some kind of large id
(like the group ID). But it only stores a single bit. It is more appropriate
to just use a single bit per port.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The names of the LAG variables in struct rtl838x_switch_priv are not self
explaining. They are even suggesting that they are dealing with information
which are actually stored in a different variable. As first step, document
their meaning.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
There is no need to check conditions in rtl83xx_lag_add()/rtl83xx_lag_del()
when they are already checked in
rtl83xx_port_lag_join()/rtl83xx_port_lag_leave().
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
It is not necessary to have a private LAG id allocation when the shared DSA
code already provides the complete infrastructure for it.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The DSA code is responsible to inform the driver about link aggregation
changes. Having a second one which behaves slightly different makes the
whole process fragile and creates hard to debug problems.
It also complicates the code because the secondary event handler can also
not rely on shared DSA state to handle things like LAG ID.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The rtl83xx_lag_can_offload() function always returned an error because
ds->num_lag_ids was never set. This basically disabled the DSA lag
configuration completely.
Drop the private n_lag variable and instead use the DSA specific one. This
ensures that all the code always has the same reference for the number of
LAGs.
Fixes: 32e5b5ee6b ("realtek: Add Link Aggregation (aka trunking) support")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Commit 8ca4caacd0 ("rockchip: Add support for RK3568 LinkEase EasePi R1")
forgot to include the SoC recipe, which leads KERNEL_LOADADDR undefined.
Fixes: 8ca4caacd0 ("rockchip: Add support for RK3568 LinkEase EasePi R1")
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/20722
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The ifname was renamed to `lan`/`wan` in commit 1f1db75432
("rockchip: make NIC name predictable for Radxa E52C/ROCK 5 ITX/ROCK 5T"),
update accordingly.
Fixes: 1f1db75432 ("rockchip: make NIC name predictable for Radxa E52C/ROCK 5 ITX/ROCK 5T")
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/20722
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Th function to set the mangement frames receive actions is only used in the
SoC specific files. They can therefore be kept local without any
declaration in headers.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20704
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The code for the RTL930x management action configuration was cleaned up
significantly for commit 75fe6b2d0b ("realtek: rtl930x: Add support for
trapping management frames"). Sync these changes to RTL931x to make it
easier to extend both implementations.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20704
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport upstream patch fixing out of order DMA access for ethernet
driver. This is relevant in the context of QoS when packets doesn't
follow linear handling by QDMA HW.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
KConfig flag have an extra whitespace for CONFIG_PHY_AIROHA_USB and
value is not ignored.
Drop the extra whitespace to correctly ignore the value on kernel
compilation.
Fixes: c5b12fc02a ("airoha: Introduce support for Airoha AN7583 SoC")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
As per #19596 - this allows eg, modifying the bootcmd etc.
This has been useful when testing on e.g the -48, where `rtk network on` is required for the SFP ports.
Signed-off-by: Joe Holden <jwh@zorins.us>
Link: https://github.com/openwrt/openwrt/pull/19913
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The ports are physically labelled in reverse order on the device.
This patch aligns logical names with physical ones.
LED order on front of device is correct after this patch.
Fixes: 9d66b8b312
Signed-off-by: Thibaut VARÈNE <hacks@slashdirt.org>
Link: https://github.com/openwrt/openwrt/pull/20528
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
After switching to 6.12, time to remove 6.6 support.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20672
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
No new reggresions was observed. Time to switch to 6.12.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20672
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The probe order for PCIe buses and devices is non-deterministic,
making the names eth0 and eth1 unpredictable (they may be swapped).
This patch fixes the names by referencing the device path using
`ucidef_set_network_device_path`.
The mapping between silkscreen labels on the board/case and OpenWrt
interface names is as follows:
- E52C
LAN: lan
WAN: wan
- ROCK 5 ITX
RJ45 1: eth0
RJ45 2: eth1
- ROCK 5T
RJ45_1: eth0
RJ45_2: eth1
For Radxa E52C, this breaks compatibility of the network config;
therefore, set DEVICE_COMPAT_VERSION to `1.1`.
Fixes: d16d2765bd ("rockchip: add support for Radxa E52C")
Fixes: 0839345211 ("rockchip: add support for Radxa ROCK 5 ITX/ITX+")
Fixes: 4a78af9876 ("rockchip: add support for Radxa ROCK 5T")
Link: https://github.com/openwrt/openwrt/issues/20202
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/20608
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Hardware:
- SoC: MediaTek MT7621DAT
- Flash: 16 MiB XM25QH128C
- RAM: 128 MiB
- WLAN: 2.4 GHz (MT7603E, 11n), 5 GHz (MediaTek MT7613BEN, 11ac)
- Ethernet: 1x10/100/1000 Mbps LAN
- Buttons: 1 Reset button, 1 WPS button
- LEDs: 5x Green
- Serial Console: unpopulated header 115200 8n1 (silkscreen on PCB)
- Power: POE 802.3af (37-57V DC)
MAC addresses:
+---------+-------------------+-----------+
| | MAC | Algorithm |
+---------+-------------------+-----------+
| LAN | 80:af:ca:xx:xx:x0 | label |
| WLAN 2g | 80:af:ca:xx:xx:x0 | label |
| WLAN 5g | 82:af:ca:xx:xx:x1 | +1 |
+---------+-------------------+-----------+
Installation:
The factory firmware is locked: you can only work with Cudy signed firmware.
Download a intermediate firmware signed by Cudy here:
https://www.cudy.com/blogs/faq/openwrt-software-download
After that, login to the router (192.168.10.254, password "admin") and install the intermediate firmware.
If you can reach LuCI or SSH now on the intermediate firmware, just use the sysupgrade image with the 'Keep settings' option turned off.
Special thanks to Daniel de Kock for starting the porting work at #16265.
Signed-off-by: Luis Mita <luis@luismita.com>
Co-Authored-By: Daniel de Kock <daniel@riot.network>
Co-Authored-By: Hauke Mehrtens <hauke@hauke-m.de>
Link: https://github.com/openwrt/openwrt/pull/20268
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Allow to configure SerDes polarity in device tree. To achieve this, add
new device tree properties that can be set in the device tree definition
of the SerDes, are read by the PCS driver during probe and are applied
upon SerDes setup.
This may be required for supporting new devices as the SerDes polarity
is usually subject to the vendors board design and defined in the
hardware profile (HWP) in the SDK. Most importantly, it is quite an
important step towards being able to setup everything on our own instead
of relying on the bootloader.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20648
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The configuration code for RTL930X already provides setting the SerDes
TX and RX PN polarity. This is covered by a function called
'..._sds_mac_link_config'. But despite its name, this function only sets
the SerDes polarity and nothing more.
Moreover, this was called always with 'not inverted' in the SerDes setup
code and thus not really allowing to be configured.
At first, streamline the SerDes polarity configuration code. Rename the
function to reflect what it actually does instead of giving the
impression of doing more. Improve the implementation of this for better
readability.
As the implementation, page, register, bits, etc. are exactly the same
for both RTL930X and RTL931X (compare [1] and [2]), move and name it
accordingly so we can also add support for RTL931X.
[1] 69d2890a2e/sources/rtk-xgs1210/src/hal/phy/phy_rtl9300.c (L1384)
[2] 69d2890a2e/sources/rtk-xgs1210/src/hal/phy/phy_rtl9310.c (L3479)
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20648
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Change return value from -EINVAL to -ENOENT for the TRX parser
workaround patch as it's better suited and it's the common exit error
for parser failing parsing for expected condition (partition not init,
zero partition found in the schema, magic values not matching)
Also this is needed for a pending upstream patch that will permit parser
to fail and be skipped for subpartitions only with the -ENOENT error.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
