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realtek: dsa: rtl93xx: Configure default QoS prioritization
RTL838x+RTL839x both configure a default QoS behavior with a default mapping. This also needs to be added to RTL93xx to ensure a consistent behavior: * Set the default mapping between DSCP and priority: prio = dscp >> 3. * Set the default mapping between internal priority and queues * Set uniform prioritization of queues (as with other SoCs) Signed-off-by: Issam Hamdi <ih@simonwunderlich.de> Co-developed-by: Sven Eckelmann <se@simonwunderlich.de> Signed-off-by: Sven Eckelmann <se@simonwunderlich.de> Link: https://github.com/openwrt/openwrt/pull/20640 Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Issam Hamdi
Robert Marko
parent
d78a2a6597
commit
22178914c6
4 changed files with 211 additions and 6 deletions
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@ -14,8 +14,8 @@ enum scheduler_type {
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WEIGHTED_ROUND_ROBIN,
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};
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int max_available_queue[] = {0, 1, 2, 3, 4, 5, 6, 7};
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int default_queue_weights[] = {1, 1, 1, 1, 1, 1, 1, 1};
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int rtldsa_max_available_queue[] = {0, 1, 2, 3, 4, 5, 6, 7};
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int rtldsa_default_queue_weights[] = {1, 1, 1, 1, 1, 1, 1, 1};
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int dot1p_priority_remapping[] = {0, 1, 2, 3, 4, 5, 6, 7};
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static void rtl839x_read_scheduling_table(int port)
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@ -324,11 +324,11 @@ static void rtl83xx_setup_prio2queue_cpu_matrix(int *max_queues)
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static void rtl83xx_setup_default_prio2queue(void)
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{
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if (soc_info.family == RTL8380_FAMILY_ID) {
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rtl838x_setup_prio2queue_matrix(max_available_queue);
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rtl838x_setup_prio2queue_matrix(rtldsa_max_available_queue);
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} else {
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rtl839x_setup_prio2queue_matrix(max_available_queue);
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rtl839x_setup_prio2queue_matrix(rtldsa_max_available_queue);
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}
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rtl83xx_setup_prio2queue_cpu_matrix(max_available_queue);
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rtl83xx_setup_prio2queue_cpu_matrix(rtldsa_max_available_queue);
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}
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/* Sets the output queue assigned to a port, the port can be the CPU-port */
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@ -508,7 +508,7 @@ static void rtl839x_config_qos(void)
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for (int port = 0; port <= soc_info.cpu_port; port++) {
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rtl83xx_set_ingress_priority(port, 0);
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rtl839x_set_scheduling_algorithm(priv, port, WEIGHTED_FAIR_QUEUE);
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rtl839x_set_scheduling_queue_weights(priv, port, default_queue_weights);
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rtl839x_set_scheduling_queue_weights(priv, port, rtldsa_default_queue_weights);
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/* Do re-marking based on outer tag */
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sw_w32_mask(0, BIT(port % 32), RTL839X_RMK_PORT_DEI_TAG_CTRL(port));
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}
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@ -562,5 +562,9 @@ void __init rtl83xx_setup_qos(struct rtl838x_switch_priv *priv)
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rtl839x_config_qos();
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rtl839x_rate_control_init(priv);
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break;
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default:
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if (priv->r->qos_init)
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priv->r->qos_init(priv);
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break;
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}
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}
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@ -510,6 +510,55 @@ typedef enum {
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#define RTL838X_SCHED_LB_CTRL(p) (0xC004 + (((p) << 7)))
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#define RTL838X_FC_P_EGR_DROP_CTRL(p) (0x6B1C + (((p) << 2)))
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#define RTL930X_REMAP_DSCP(p) (0x9B04 + (((p) / 10) * 4))
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#define RTL931X_REMAP_DSCP(p) (0x9034 + (((p) / 10) * 4))
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#define RTL93XX_REMAP_DSCP_INTPRI_DSCP_OFFSET(p) \
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(((p) % 10) * 3)
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#define RTL93XX_REMAP_DSCP_INTPRI_DSCP_MASK(index) \
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(0x7 << RTL93XX_REMAP_DSCP_INTPRI_DSCP_OFFSET(index))
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#define RTL930X_PORT_TBL_IDX_CTRL(port) (0x9B20 + (((port) / 16) * 4))
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#define RTL931X_PORT_TBL_IDX_CTRL(port) (0x9064 + (((port) / 16) * 4))
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#define RTL93XX_PORT_TBL_IDX_CTRL_IDX_OFFSET(port) \
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(((port) & 0xF) << 1)
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#define RTL93XX_PORT_TBL_IDX_CTRL_IDX_MASK(port) \
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(0x3 << RTL93XX_PORT_TBL_IDX_CTRL_IDX_OFFSET(port))
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#define RTL93XX_PRI_SEL_GROUP_0 (0)
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#define RTL93XX_PRI_SEL_GROUP_1 (1)
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#define RTL930X_PRI_SEL_TBL_CTRL(group) (0x9B28 + ((group) * 4))
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#define RTL931X_PRI_SEL_TBL_CTRL(group) (0x9074 + ((group) * 8))
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#define RTL931X_PRI_SEL_TBL_CTRL_1BR_MASK GENMASK(15, 12)
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#define RTL931X_PRI_SEL_TBL_CTRL_MPLS_MASK GENMASK(11, 8)
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#define RTL931X_PRI_SEL_TBL_CTRL_11E_MASK GENMASK(7, 4)
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#define RTL931X_PRI_SEL_TBL_CTRL_TUNNEL_MASK GENMASK(3, 0)
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#define RTL93XX_PRI_SEL_TBL_CTRL_ROUT_MASK GENMASK(31, 28)
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#define RTL93XX_PRI_SEL_TBL_CTRL_PROT_VLAN_MASK GENMASK(27, 24)
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#define RTL93XX_PRI_SEL_TBL_CTRL_MAC_VLAN_MASK GENMASK(23, 20)
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#define RTL93XX_PRI_SEL_TBL_CTRL_OTAG_MASK GENMASK(19, 16)
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#define RTL93XX_PRI_SEL_TBL_CTRL_ITAG_MASK GENMASK(15, 12)
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#define RTL93XX_PRI_SEL_TBL_CTRL_DSCP_MASK GENMASK(11, 8)
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#define RTL93XX_PRI_SEL_TBL_CTRL_VACL_MASK GENMASK(7, 4)
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#define RTL93XX_PRI_SEL_TBL_CTRL_PORT_MASK GENMASK(3, 0)
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/* port: 0-23, index: 0-7 */
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#define RTL930X_SCHED_PORT_Q_CTRL_SET0(port, index) \
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(0x3D48 + ((port) * 384) + ((index) * 4))
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/* port: 24-27, index: 0-11 */
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#define RTL930X_SCHED_PORT_Q_CTRL_SET1(port, index) \
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((0xE860 + ((port) - 24) * 48) + ((index) * 4))
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/* port: 0-51, index: 0-7 */
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#define RTL931X_SCHED_PORT_Q_CTRL_SET0(port, index) \
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(0x2888 + ((port) << 5) + ((index) * 4))
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/* port: 52-55, index: 0-11 */
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#define RTL931X_SCHED_PORT_Q_CTRL_SET1(port, index) \
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((0x2F08 + ((port) - 52) * 48) + ((index) * 4))
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#define RTL930X_QM_INTPRI2QID_CTRL (0xA320)
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#define RTL931X_QM_INTPRI2QID_CTRL (0xA9D0)
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/* Debug features */
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#define RTL930X_STAT_PRVTE_DROP_COUNTER0 (0xB5B8)
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@ -633,6 +682,7 @@ typedef enum {
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#define MAX_ROUTER_MACS 64
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#define L3_EGRESS_DMACS 2048
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#define MAX_SMACS 64
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#define DSCP_MAP_MAX 64
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enum phy_type {
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PHY_NONE = 0,
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@ -1139,6 +1189,7 @@ struct rtl838x_reg {
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void (*set_distribution_algorithm)(int group, int algoidx, u32 algomask);
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void (*set_receive_management_action)(int port, rma_ctrl_t type, action_type_t action);
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void (*led_init)(struct rtl838x_switch_priv *priv);
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void (*qos_init)(struct rtl838x_switch_priv *priv);
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};
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struct rtl838x_switch_priv {
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@ -1204,4 +1255,7 @@ struct rtl838x_switch_priv {
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void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv);
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void rtl930x_dbgfs_init(struct rtl838x_switch_priv *priv);
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extern int rtldsa_max_available_queue[];
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extern int rtldsa_default_queue_weights[];
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#endif /* _RTL838X_H */
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@ -2515,6 +2515,78 @@ static void rtl930x_led_init(struct rtl838x_switch_priv *priv)
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dev_dbg(dev, "%08x: %08x\n", 0xbb00cc00 + i * 4, sw_r32(0xcc00 + i * 4));
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}
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static void rtldsa_930x_qos_set_group_selector(int port, int group)
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{
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sw_w32_mask(RTL93XX_PORT_TBL_IDX_CTRL_IDX_MASK(port),
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group << RTL93XX_PORT_TBL_IDX_CTRL_IDX_OFFSET(port),
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RTL930X_PORT_TBL_IDX_CTRL(port));
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}
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static void rtldsa_930x_qos_setup_default_dscp2queue_map(void)
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{
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u32 queue;
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/* The default mapping between dscp and queue is based on
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* the first 3 bits indicate the precedence (prio = dscp >> 3).
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*/
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for (int i = 0; i < DSCP_MAP_MAX; i++) {
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queue = (i >> 3) << RTL93XX_REMAP_DSCP_INTPRI_DSCP_OFFSET(i);
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sw_w32_mask(RTL93XX_REMAP_DSCP_INTPRI_DSCP_MASK(i),
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queue, RTL930X_REMAP_DSCP(i));
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}
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}
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static void rtldsa_930x_qos_prio2queue_matrix(int *min_queues)
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{
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u32 v = 0;
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for (int i = 0; i < MAX_PRIOS; i++)
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v |= i << (min_queues[i] * 3);
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sw_w32(v, RTL930X_QM_INTPRI2QID_CTRL);
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}
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static void rtldsa_930x_qos_set_scheduling_queue_weights(struct rtl838x_switch_priv *priv)
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{
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struct dsa_port *dp;
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u32 addr;
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dsa_switch_for_each_user_port(dp, priv->ds) {
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for (int q = 0; q < 8; q++) {
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if (dp->index < 24)
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addr = RTL930X_SCHED_PORT_Q_CTRL_SET0(dp->index, q);
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else
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addr = RTL930X_SCHED_PORT_Q_CTRL_SET1(dp->index, q);
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sw_w32(rtldsa_default_queue_weights[q], addr);
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}
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}
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}
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static void rtldsa_930x_qos_init(struct rtl838x_switch_priv *priv)
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{
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struct dsa_port *dp;
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u32 v;
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/* Assign all the ports to the Group-0 */
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dsa_switch_for_each_user_port(dp, priv->ds)
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rtldsa_930x_qos_set_group_selector(dp->index, 0);
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rtldsa_930x_qos_prio2queue_matrix(rtldsa_max_available_queue);
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/* configure priority weights */
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v = 0;
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v |= FIELD_PREP(RTL93XX_PRI_SEL_TBL_CTRL_PORT_MASK, 3);
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v |= FIELD_PREP(RTL93XX_PRI_SEL_TBL_CTRL_DSCP_MASK, 5);
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v |= FIELD_PREP(RTL93XX_PRI_SEL_TBL_CTRL_ITAG_MASK, 6);
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v |= FIELD_PREP(RTL93XX_PRI_SEL_TBL_CTRL_OTAG_MASK, 7);
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sw_w32(v, RTL930X_PRI_SEL_TBL_CTRL(0));
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rtldsa_930x_qos_setup_default_dscp2queue_map();
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rtldsa_930x_qos_set_scheduling_queue_weights(priv);
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}
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const struct rtl838x_reg rtl930x_reg = {
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.mask_port_reg_be = rtl838x_mask_port_reg,
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.set_port_reg_be = rtl838x_set_port_reg,
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@ -2601,4 +2673,5 @@ const struct rtl838x_reg rtl930x_reg = {
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.enable_learning = rtldsa_930x_enable_learning,
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.enable_flood = rtldsa_930x_enable_flood,
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.set_receive_management_action = rtldsa_930x_set_receive_management_action,
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.qos_init = rtldsa_930x_qos_init,
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};
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@ -1644,6 +1644,79 @@ static void rtldsa_931x_led_init(struct rtl838x_switch_priv *priv)
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dev_dbg(dev, "%08x: %08x\n", 0xbb000600 + i * 4, sw_r32(0x0600 + i * 4));
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}
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static void rtldsa_931x_qos_set_group_selector(int port, int group)
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{
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sw_w32_mask(RTL93XX_PORT_TBL_IDX_CTRL_IDX_MASK(port),
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group << RTL93XX_PORT_TBL_IDX_CTRL_IDX_OFFSET(port),
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RTL931X_PORT_TBL_IDX_CTRL(port));
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}
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static void rtldsa_931x_qos_setup_default_dscp2queue_map(void)
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{
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u32 queue;
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/* The default mapping between dscp and queue is based on
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* the first 3 bits indicate the precedence (prio = dscp >> 3).
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*/
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for (int i = 0; i < DSCP_MAP_MAX; i++) {
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queue = (i >> 3) << RTL93XX_REMAP_DSCP_INTPRI_DSCP_OFFSET(i);
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sw_w32_mask(RTL93XX_REMAP_DSCP_INTPRI_DSCP_MASK(i),
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queue, RTL931X_REMAP_DSCP(i));
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}
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}
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static void rtldsa_931x_qos_prio2queue_matrix(int *min_queues)
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{
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u32 v = 0;
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for (int i = 0; i < MAX_PRIOS; i++)
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v |= i << (min_queues[i] * 3);
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sw_w32(v, RTL931X_QM_INTPRI2QID_CTRL);
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}
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static void rtldsa_931x_qos_set_scheduling_queue_weights(struct rtl838x_switch_priv *priv)
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{
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struct dsa_port *dp;
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u32 addr;
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dsa_switch_for_each_user_port(dp, priv->ds) {
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for (int q = 0; q < 8; q++) {
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if (dp->index < 51)
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addr = RTL931X_SCHED_PORT_Q_CTRL_SET0(dp->index, q);
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else
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addr = RTL931X_SCHED_PORT_Q_CTRL_SET1(dp->index, q);
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sw_w32(rtldsa_default_queue_weights[q], addr);
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}
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}
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}
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static void rtldsa_931x_qos_init(struct rtl838x_switch_priv *priv)
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{
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struct dsa_port *dp;
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u32 v;
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/* Assign all the ports to the Group-0 */
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dsa_switch_for_each_user_port(dp, priv->ds)
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rtldsa_931x_qos_set_group_selector(dp->index, 0);
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rtldsa_931x_qos_prio2queue_matrix(rtldsa_max_available_queue);
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/* configure priority weights */
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v = 0;
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v |= FIELD_PREP(RTL93XX_PRI_SEL_TBL_CTRL_PORT_MASK, 3);
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v |= FIELD_PREP(RTL93XX_PRI_SEL_TBL_CTRL_DSCP_MASK, 5);
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v |= FIELD_PREP(RTL93XX_PRI_SEL_TBL_CTRL_ITAG_MASK, 6);
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v |= FIELD_PREP(RTL93XX_PRI_SEL_TBL_CTRL_OTAG_MASK, 7);
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sw_w32(v, RTL931X_PRI_SEL_TBL_CTRL(0) + 4);
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sw_w32(0, RTL931X_PRI_SEL_TBL_CTRL(0));
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rtldsa_931x_qos_setup_default_dscp2queue_map();
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rtldsa_931x_qos_set_scheduling_queue_weights(priv);
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}
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const struct rtl838x_reg rtl931x_reg = {
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.mask_port_reg_be = rtl839x_mask_port_reg_be,
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.set_port_reg_be = rtl839x_set_port_reg_be,
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@ -1710,4 +1783,5 @@ const struct rtl838x_reg rtl931x_reg = {
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.enable_learning = rtldsa_931x_enable_learning,
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.enable_flood = rtldsa_931x_enable_flood,
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.set_receive_management_action = rtldsa_931x_set_receive_management_action,
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.qos_init = rtldsa_931x_qos_init,
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};
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