Usage of strlcpy results in a compilation error. strscpy is preferred
anyways and equivalent for our case.
Signed-off-by: David Bauer <mail@david-bauer.net>
This is an automatically generated commit which aids following Kernel patch
history, as git will see the move and copy as a rename thus defeating the
purpose.
For the original discussion see:
https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
This is an automatically generated commit.
When doing `git bisect`, consider `git bisect --skip`.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
CMCC PZ-L8 is a 2.4/5 GHz band 11ax (Wi-Fi 6) router, based on IPQ5000.
Specifications:
- SoC : Qualcomm IPQ5000
- RAM : Integrated 256MiB DDR3L
- Flash : 128 MiB SPI-NAND (ESMT F50D1G41LB)
- WLAN : 2.4/5 GHz 2T2R
- 2.4 GHz : Qualcomm IPQ5000 (SoC)
- 5 GHz : Qualcomm Atheros QCN6102
- Ethernet : 4x 10/100/1000 Mbps
- switch : Qualcomm Atheros QCA8337
- LEDs/Keys (GPIO) : 2x LEDs, 2x Keys
- UART : Through-hole on PCB, 4pins in the middle of the black aluminum heat sink
- assignment : 3.3V, GND,TX, RX (from left to right)
- settings : 115200n8
- Power : 12 VDC, 1 A
Flashing Instructions:
1. SSH Method
(1) Enable SSH on the stock firmware
a. Version 501.8 and 501.9:
Log in to http://192.168.10.1 with the password on the sticker
Append "/admin/system/admin" to the URL and press Enter
Delete "Dropbear instance", click "Add instance", then "Save and Apply"
Reboot the router
b. Version 501.11 and 501.12:
While the router is running the stock firmware, press and hold the reset button for 20-30 seconds
Open http://192.168.10.1:56781 and login with username "root" and the password on the sticker
Run "vi /etc/config/dropbear" and delete the line "option enable '0'"
Reboot the router
(2) Upload the factory.ubi file to router's /tmp directory (using scp or wget)
and execute the following commands in the router's shell
export rootfs=$(cat /proc/mtd | grep rootfs | grep -v _ | cut -d: -f1)
ubidetach -f -p /dev/${rootfs}
ubiformat /dev/${rootfs} -y -f /tmp/factory.ubi
2. U-Boot Method using UBI Image
Place the factory.ubi file on your TFTP server, enter U-Boot CLI and exec these commands
tftpboot <your_tftp_server_ip>:factory.ubi
flash rootfs
reset
3. U-Boot Method using initramfs Image
(1) Place the openwrt-*-initramfs-fit-uImage.itb file on your TFTP server
and rename it to initramfs.bin
(2) Enable serial console, enter to U-Boot CLI and exec these commands
tftpboot <your_tftp_server_ip>:initramfs.bin
bootm
(3) Once boot completed, upload the sysupgrade.bin file to router's /tmp directory
(using scp or wget) and execute the following command in openwrt shell
sysupgrade -n /tmp/sysupgrade.bin
Switching to the Stock Firmware:
Please follow the commit 3b7d72bc2e
Partition Layout (Stock Firmware):
0x000000000000-0x000000080000 : "0:SBL1"
0x000000080000-0x000000100000 : "0:MIBIB"
0x000000100000-0x000000140000 : "0:BOOTCONFIG"
0x000000140000-0x000000180000 : "0:BOOTCONFIG1"
0x000000180000-0x000000280000 : "0:QSEE"
0x000000280000-0x000000380000 : "0:QSEE_1"
0x000000380000-0x0000003c0000 : "0:DEVCFG"
0x0000003c0000-0x000000400000 : "0:DEVCFG_1"
0x000000400000-0x000000440000 : "0:CDT"
0x000000440000-0x000000480000 : "0:CDT_1"
0x000000480000-0x000000500000 : "0:APPSBLENV"
0x000000500000-0x000000640000 : "0:APPSBL"
0x000000640000-0x000000780000 : "0:APPSBL_1"
0x000000780000-0x000000880000 : "0:ART"
0x000000880000-0x000000900000 : "0:TRAINING"
0x000000900000-0x000004300000 : "rootfs"
0x000004300000-0x000007d00000 : "rootfs_1"
Notes:
This device is almost the same as ELECOM WRC-X3000GS2, including partition layout and the dual-boot feature.
Known Issues:
- All Wi-Fi related peripherals are disabled in device tree, since 256 MiB RAM is too few for ath11k.
- This device has another version with nand flash FM25SL01, which is not supported at the moment.
https://github.com/immortalwrt/immortalwrt/blob/master/target/linux/mediatek/patches-6.12/342-mtd-spinand-Support-fmsh.patch
MAC Addresses:
Interface MAC Address Location (binary)
LAN A4:39:B6:xx:xx:9D (0:ART, 0x00-0x05)
WAN A4:39:B6:xx:xx:9E (0:ART, 0x06-0x0B)
2.4 GHz A4:39:B6:xx:xx:9F (0:ART, 0x0C-0x11)
5 GHz A4:39:B6:xx:xx:A0 (0:ART, 0x12-0x17)
Signed-off-by: Chang Liu <jssqliuchang@gmail.com>
The "old" QCA8084 PHY driver does not implement 10g-qxgmii support.
This is blocking several devices which use the QCA8084 form being
merged. Qualcomm has provided updated drivers for the MAC (ppe), PCS,
and PHY via github. We only need to update the PHY driver.
Update the QCA8084 PHY driver using the patches provided by Qualcomm.
Re-organize the patches so that the changes go into the existing
patches. The SERDES functionality is new, so it gets new patches. This
is sufficient to enable 10g-qxgmii on ipq95xx platforms.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20721
Signed-off-by: Robert Marko <robimarko@gmail.com>
Replace Airoha AN7583 pinctrl patch with upstream version as it has been
accepted upstream. Add the related kernel version tag to identify it.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The unit-address of the ubi partition was @a9c0000 but the partition
actually starts at offset 0x0ad00000. Ideally they should match, so
align them.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20733
Signed-off-by: Robert Marko <robimarko@gmail.com>
The name "is_lagmember" implies that the port is part of a LAG. But this
information is already stored in lagmembers. In reality, it is stored the
non-primary LAG members. Renaming it accordingly, makes the code a lot more
readable
Also the type (u32 array) looks like it would contain some kind of large id
(like the group ID). But it only stores a single bit. It is more appropriate
to just use a single bit per port.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The names of the LAG variables in struct rtl838x_switch_priv are not self
explaining. They are even suggesting that they are dealing with information
which are actually stored in a different variable. As first step, document
their meaning.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
There is no need to check conditions in rtl83xx_lag_add()/rtl83xx_lag_del()
when they are already checked in
rtl83xx_port_lag_join()/rtl83xx_port_lag_leave().
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
It is not necessary to have a private LAG id allocation when the shared DSA
code already provides the complete infrastructure for it.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The DSA code is responsible to inform the driver about link aggregation
changes. Having a second one which behaves slightly different makes the
whole process fragile and creates hard to debug problems.
It also complicates the code because the secondary event handler can also
not rely on shared DSA state to handle things like LAG ID.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The rtl83xx_lag_can_offload() function always returned an error because
ds->num_lag_ids was never set. This basically disabled the DSA lag
configuration completely.
Drop the private n_lag variable and instead use the DSA specific one. This
ensures that all the code always has the same reference for the number of
LAGs.
Fixes: 32e5b5ee6b ("realtek: Add Link Aggregation (aka trunking) support")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Commit 8ca4caacd0 ("rockchip: Add support for RK3568 LinkEase EasePi R1")
forgot to include the SoC recipe, which leads KERNEL_LOADADDR undefined.
Fixes: 8ca4caacd0 ("rockchip: Add support for RK3568 LinkEase EasePi R1")
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/20722
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The ifname was renamed to `lan`/`wan` in commit 1f1db75432
("rockchip: make NIC name predictable for Radxa E52C/ROCK 5 ITX/ROCK 5T"),
update accordingly.
Fixes: 1f1db75432 ("rockchip: make NIC name predictable for Radxa E52C/ROCK 5 ITX/ROCK 5T")
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/20722
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Th function to set the mangement frames receive actions is only used in the
SoC specific files. They can therefore be kept local without any
declaration in headers.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20704
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The code for the RTL930x management action configuration was cleaned up
significantly for commit 75fe6b2d0b ("realtek: rtl930x: Add support for
trapping management frames"). Sync these changes to RTL931x to make it
easier to extend both implementations.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20704
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport upstream patch fixing out of order DMA access for ethernet
driver. This is relevant in the context of QoS when packets doesn't
follow linear handling by QDMA HW.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
KConfig flag have an extra whitespace for CONFIG_PHY_AIROHA_USB and
value is not ignored.
Drop the extra whitespace to correctly ignore the value on kernel
compilation.
Fixes: c5b12fc02a ("airoha: Introduce support for Airoha AN7583 SoC")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
As per #19596 - this allows eg, modifying the bootcmd etc.
This has been useful when testing on e.g the -48, where `rtk network on` is required for the SFP ports.
Signed-off-by: Joe Holden <jwh@zorins.us>
Link: https://github.com/openwrt/openwrt/pull/19913
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The ports are physically labelled in reverse order on the device.
This patch aligns logical names with physical ones.
LED order on front of device is correct after this patch.
Fixes: 9d66b8b312
Signed-off-by: Thibaut VARÈNE <hacks@slashdirt.org>
Link: https://github.com/openwrt/openwrt/pull/20528
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
After switching to 6.12, time to remove 6.6 support.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20672
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
No new reggresions was observed. Time to switch to 6.12.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20672
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The probe order for PCIe buses and devices is non-deterministic,
making the names eth0 and eth1 unpredictable (they may be swapped).
This patch fixes the names by referencing the device path using
`ucidef_set_network_device_path`.
The mapping between silkscreen labels on the board/case and OpenWrt
interface names is as follows:
- E52C
LAN: lan
WAN: wan
- ROCK 5 ITX
RJ45 1: eth0
RJ45 2: eth1
- ROCK 5T
RJ45_1: eth0
RJ45_2: eth1
For Radxa E52C, this breaks compatibility of the network config;
therefore, set DEVICE_COMPAT_VERSION to `1.1`.
Fixes: d16d2765bd ("rockchip: add support for Radxa E52C")
Fixes: 0839345211 ("rockchip: add support for Radxa ROCK 5 ITX/ITX+")
Fixes: 4a78af9876 ("rockchip: add support for Radxa ROCK 5T")
Link: https://github.com/openwrt/openwrt/issues/20202
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/20608
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Hardware:
- SoC: MediaTek MT7621DAT
- Flash: 16 MiB XM25QH128C
- RAM: 128 MiB
- WLAN: 2.4 GHz (MT7603E, 11n), 5 GHz (MediaTek MT7613BEN, 11ac)
- Ethernet: 1x10/100/1000 Mbps LAN
- Buttons: 1 Reset button, 1 WPS button
- LEDs: 5x Green
- Serial Console: unpopulated header 115200 8n1 (silkscreen on PCB)
- Power: POE 802.3af (37-57V DC)
MAC addresses:
+---------+-------------------+-----------+
| | MAC | Algorithm |
+---------+-------------------+-----------+
| LAN | 80:af:ca:xx:xx:x0 | label |
| WLAN 2g | 80:af:ca:xx:xx:x0 | label |
| WLAN 5g | 82:af:ca:xx:xx:x1 | +1 |
+---------+-------------------+-----------+
Installation:
The factory firmware is locked: you can only work with Cudy signed firmware.
Download a intermediate firmware signed by Cudy here:
https://www.cudy.com/blogs/faq/openwrt-software-download
After that, login to the router (192.168.10.254, password "admin") and install the intermediate firmware.
If you can reach LuCI or SSH now on the intermediate firmware, just use the sysupgrade image with the 'Keep settings' option turned off.
Special thanks to Daniel de Kock for starting the porting work at #16265.
Signed-off-by: Luis Mita <luis@luismita.com>
Co-Authored-By: Daniel de Kock <daniel@riot.network>
Co-Authored-By: Hauke Mehrtens <hauke@hauke-m.de>
Link: https://github.com/openwrt/openwrt/pull/20268
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Allow to configure SerDes polarity in device tree. To achieve this, add
new device tree properties that can be set in the device tree definition
of the SerDes, are read by the PCS driver during probe and are applied
upon SerDes setup.
This may be required for supporting new devices as the SerDes polarity
is usually subject to the vendors board design and defined in the
hardware profile (HWP) in the SDK. Most importantly, it is quite an
important step towards being able to setup everything on our own instead
of relying on the bootloader.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20648
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The configuration code for RTL930X already provides setting the SerDes
TX and RX PN polarity. This is covered by a function called
'..._sds_mac_link_config'. But despite its name, this function only sets
the SerDes polarity and nothing more.
Moreover, this was called always with 'not inverted' in the SerDes setup
code and thus not really allowing to be configured.
At first, streamline the SerDes polarity configuration code. Rename the
function to reflect what it actually does instead of giving the
impression of doing more. Improve the implementation of this for better
readability.
As the implementation, page, register, bits, etc. are exactly the same
for both RTL930X and RTL931X (compare [1] and [2]), move and name it
accordingly so we can also add support for RTL931X.
[1] 69d2890a2e/sources/rtk-xgs1210/src/hal/phy/phy_rtl9300.c (L1384)
[2] 69d2890a2e/sources/rtk-xgs1210/src/hal/phy/phy_rtl9310.c (L3479)
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20648
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Change return value from -EINVAL to -ENOENT for the TRX parser
workaround patch as it's better suited and it's the common exit error
for parser failing parsing for expected condition (partition not init,
zero partition found in the schema, magic values not matching)
Also this is needed for a pending upstream patch that will permit parser
to fail and be skipped for subpartitions only with the -ENOENT error.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This commit adds support for TP-LINK BE450.
Device specification
--------------------
SoC Type: MediaTek MT7988D, Cortex-A73, 64-bit
RAM: 512MB
Flash: SPI NAND GigaDevice (128 MiB)
Ethernet: MediaTek MT7531AE (3 Ports) + 2.5GbE (internal MT7988 phy) + 10GbE (RTL8261N)
WLAN: MT7992
WLAN 2g: MediaTek MT7975N, b/g/n/ax/be, MIMO 4x4
WLAN 5g: MediaTek MT7979N, a/n/ac/ax/be, MIMO 4x4
LEDs: 8 LEDs, 1 status blue, 2x WIFI blue, 2x Internet
blue/orange, 1 LAN blue, 1 usb blue, 1 wps blue, gpio-controlled
Button: 2 (Reset, WPS)
USB port: Yes
Power: 12 VDC, 2 A
Connector: Barrel
Bootloader: Main U-Boot - U-Boot 2023.10-rc4. Additionally, ubi0
partition contain "seconduboot" (also U-Boot 2023.10-rc4)
Serial console (UART), unpopulated, located near the power connector
---------------------
heatsink
| |
| |
| | +----+-----+------+-------+ +-----------------+
| | | TX | RX | GND | +3.3V | | power connector |
+---+ +----+-----+------+-------+ +-----------------+
|
Don't connect ----+
Disassemble: rm the 2 screws at the bottom and the one at the backside.
un-clip the case starting at the edge above the LEDs.
Installation (UART)
-------------------
1. Place OpenWrt initramfs image on tftp server with IP 192.168.1.2
2. Attach UART, switch on the router and interrupt the boot process by
pressing 'Ctrl-C'
3. Load and run OpenWrt initramfs image:
tftpboot 0x50000000 openwrt-mediatek-filogic-tplink_be450-initramfs-kernel.bin && bootm 0x50000000
4. Run 'sysupgrade -n' with the sysupgrade OpenWrt image
Note: the 10GbE (RTL8261N) is only working if reverting this Realtek target specific commit:
b77fa45d12
The second ubi partition (ubi1) is empty and there is no known
dual-partition mechanism, neither in u-boot nor in the stock firmware.
NMBM is not used.
Not Working: WED, if activated, MT7992 isn't recognized any more.
Signed-off-by: Dirk Buchwalder <buchwalder@posteo.de>
Link: https://github.com/openwrt/openwrt/pull/20398
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Return 0 if the current mtd is inactive or no valid header/rootfs found,
instead of -ENODEV.
Linux Kernel 6.7 and later versions handle all errors returned by mtd
parsers, including -ENODEV as error. So '0' needs to be returned if no
child partitions were not parsed.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20697
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Also the MT7987 RFB accidentally already set the not-yet-existing
mt798x-2p5g-phy-firmware-internal package as one of the DEVICE_PACKAGES.
This currently breaks the build, so remove it for now. Also remove stray
'blkid' package from DEVICE_PACKAGES which was accidentally copied from
MediaTek's SDK.
Fixes: 9de7189ed4 ("mediatek: build image for MT7987 RFB")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
The Plasma Cloud MCX3 Media Converter is a 3 port multi-GBit switch with
2x 10/100/1000/2500BaseT Ethernet ports and 1x SFP+ module slot.
Hardware:
- RTL9302C SoC
- Macronix MX25L25645G (32MB flash)
- Winbond W632GU6rB-11 (256MB DDR3 SDRAM)
- RTL8224 4x 10m/100m/1/2.5 Gigabit PHY
- IC+ IP802AR POE+ PSE controller
The media converter is powered by 54 Volts 1.2A barrel connector. The
internal TTL serial connector can be used to access the terminal. Pins from
1: TX RX (unused) GND. Serial connection is via 115200 baud, 8N1.
A reset button is accessible through a hole next to the SFP+ module slot.
Installation
------------
* The device can be flashed by using sysupgrade command. Either from the
original vendor firmware or using an initramfs (see "Debug")
* Connect serial as per the layout above. Connection parameters: 115200 8N1
* The image must be copied using scp to /tmp of the device
scp openwrt-realtek-rtl930x-plasmacloud_mcx3-squashfs-sysupgrade.bin root@[IP address of the device]:/tmp/
* start sysupgrade without saving the original vendor configuration
sysupgrade -n /tmp/openwrt-realtek-rtl930x-plasmacloud_mcx3-squashfs-sysupgrade.bin
Installation via u-boot
-----------------------
If you have an TFTP server connected to the switch, it is possible to
directly install the device using the factory image from u-boot
# setup networking and IP of TFP server
rtk network on
setenv ipaddr 10.100.100.99
setenv serverip 10.100.100.20
# get factory image
tftp 0x84000000 factory.bin
# erase firmware partitions
sf probe 0
sf erase 0x100000 0x01f00000
# write firmware to both partitions
sf write ${fileaddr} 0x100000 ${filesize}
sf write ${fileaddr} 0x1080000 ${filesize}
# adjust the boot commands
setenv bootargs "mtdparts=spi0.0:896k(u-boot),64k(u-boot-env),64k(u-boot-env2),15872k(inactive),15872k(firmware2)"
setenv bootcmd "rtk init; bootm 0xb5080000"
# restart
reset
Debug
-----
* Connect serial as per the layout above. Connection parameters: 115200 8N1.
* A tftp server is required, tftpd-hpa works well.
* Power the device, at U-Boot start rapidly hit Esc key to stop autoboot
* Enable network:
rtk network on
* Change ip address of device:
setenv ipaddr 192.168.1.6
* Download initramfs from TFTP server:
tftpboot 0x84000000 192.168.1.111:openwrt-realtek-rtl930x-plasmacloud_mcx3-initramfs-kernel.bin
* Boot loaded file:
bootm 0x84000000
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20625
Signed-off-by: Robert Marko <robimarko@gmail.com>
Because the firmware has not yet been accepted in linux-firmware we
cannot yet package mt7987-2p5g-phy-firmware-internal. Remove it from
DEVICE_PACKAGES of the BPi-R4-mini until the an upcoming linux-firmware
release will come with this firmware included, allowing us to then
create that package.
Fixes: 8b6c6978d6 ("mediatek: add support for BananaPi BPi-R4 Lite")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
The RTL930x and RTL931x have an ingress and egress bandwidth controller for
each port. They can can be used to reduce the throughput for each port.
They can be programmed via the the DSA flower offloading capabilities. Only
a limited functionality (bytes based rate limiter for ingress/egress) is
supported.
With kmod-sched-act-police, kmod-sched-flower and tc installed, each port
can have its ingress/egress rate limit applied in hardware using:
# tc qdisc del dev lan1 clsact
tc qdisc add dev lan1 clsact
tc filter add dev lan1 ingress flower skip_sw action police rate 100mbit burst 64k conform-exceed drop
tc filter add dev lan1 egress flower skip_sw action police rate 150mbit burst 64k conform-exceed drop
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20663
Signed-off-by: Robert Marko <robimarko@gmail.com>
On RTL930x, each SerDes pair shares a set of PLLs with different
capabilities (LC PLL: 1G/2.5G/10G, ring PLL: 1G/2.5G). In principle,
this allows any combination of speeds on a SerDes pair. However, it
creates a special case when trying to configure a SerDes for 10G while
the LC PLL is already in use at a slower speed for the neighbor SerDes.
The current implementation just gives up in that case. Instead, free up
the LC PLL by reconfiguring the neighbor SerDes to the ring PLL.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/20568
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit fixes mistaken executable bit on dts files.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/20676
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
