Added support to boot the kernel from alternate partition
Change-Id: I90e09e61293581347f48b6bd4d00982c81d7d9a8
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
1. Added emmc clk reset during mmc deinitialization to
avoid the mmc init failure in kernal bootup.
2. Clock has been configured to 192 Mhz for SDHCI mode
3. Proper register is used for disabling emmc clock
Change-Id: Id21e294380ee904027e5d6d2b2929acbd7bac672
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
This change is necessary as an additional 2 MB is
allocated as reserved memory for TZ_APPS exposed
in qseecom driver and we must notify the same
boundary as FDT_HIGH to uboot.
Without this change, the board gets stuck in uboot
with starting kernel message during boot up.
Change-Id: I6653d3c3dbac97cdf38a41d84d0b401d462cf5ce
Signed-off-by: speriaka <speriaka@codeaurora.org>
Using of Dcache invalidate all resulted in stack which
was dirty being invalidated. Hence the return address stored
in stack wasn't flushed and this caused issues. Reverting to
invalidate_dcache_range.
Change-Id: I382e07a3a81885ab02c9eae38196d3aa3ba8b086
Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
During kernel bootup, dcache is enabled to reduce boot time.
When CONFIG_SYS_DCACHE_OFF macro is defined, dcache will not
be enabled.
Change-Id: I1830b467f2948250f5e7a676dd0f16a025e7b229
Signed-off-by: Sasirekaa Madhesu <smadhesu@codeaurora.org>
Software SPI reset mode can be trigger from 4-Byte Address mode
in flash W25Q256JW.
Change-Id: I3f8ec46c2732c07a7af0cc7331102334413067ba
Signed-off-by: Santan Kumar <santank@codeaurora.org>
Enable or disable of cache functions provided by board.
This should override the default functions, hence should not be
__weak function definition in board command files.
Change-Id: I676c1f05975c723a88a0cbd2596e907fcf089eff
Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
This kw issue occurred with below message:
"Use of free memory (access) - possible".
In order to fix this issue, we have removed all
dereferenced buffer after freeing the buffer..
Change-Id: I080c45b17397333c3f897b960bdf6fca01b7a53e
Signed-off-by: Avinash Pandey <avinasv@codeaurora.org>
U-Boot now has dcache turned on. This requires cache flushing to
be performed before executing smc instrution. There are calls which
are made to TZ with huge buffer (such as kernel image for authentication).
Flushing and invalidating by address for such huge buffer will have
a performance impact, as the size of buffer is vastly bigger than
the cache size itself. Hence performing a flush of the entire cache
as opposed to performing cache flush with a start and end address.
Change-Id: If90a49d240ecf021ac9714025b6de0cce3fb9fc8
Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
Since OCR value is changed,1ms delay is added to
give cards time to respond.
Change-Id: I18bddbc9d01ab2c62529c9f2065331f83b7ecca9
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
