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ipq40xx: Added emmc clk reset during mmc deinit

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1. Added emmc clk reset during mmc deinitialization to 
avoid the mmc init failure in kernal bootup. 
2. Clock has been configured to 192 Mhz for SDHCI mode
3. Proper register is used for disabling emmc clock

Change-Id: Id21e294380ee904027e5d6d2b2929acbd7bac672
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
This commit is contained in:
Rajkumar Ayyasamy 2018-04-16 15:47:13 +05:30
parent 35992873a2
commit 5a2ad95d79
2 changed files with 15 additions and 3 deletions
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4
board/qca/arm/ipq40xx/ipq40xx.c
View file

@ -248,7 +248,7 @@ int board_eth_init(bd_t *bis)
void emmc_clock_reset(void)
{
writel(0x1, GCC_SDCC1_BCR);
udelay(10);
udelay(100);
writel(0x0, GCC_SDCC1_BCR);
}
@ -315,6 +315,8 @@ int board_mmc_init(bd_t *bis)
void board_mmc_deinit(void)
{
emmc_clock_reset();
udelay(10);
emmc_clock_disable();
}
#endif

14
drivers/clk/ipq40xx_clk.c
View file

@ -50,11 +50,21 @@ void emmc_clock_config(int mode)
writel(0x1, GCC_SDCC1_APPS_CBCR);
udelay(10);
}
if (mode == MMC_DATA_TRANSFER_SDHCI_MODE) {
/* Set root clock generator to bypass mode */
writel(0x0, GCC_SDCC1_APPS_CBCR);
udelay(10);
/* Choose divider for 192MHz */
writel(0x0, GCC_SDCC1_MISC);
/* Enable root clock generator */
writel(0x1, GCC_SDCC1_APPS_CBCR);
udelay(10);
}
}
void emmc_clock_disable(void)
{
/* Clear divider */
writel(0x0, GCC_SDCC1_MISC);
writel(0x0, GCC_SDCC1_APPS_CBCR);
udelay(10);
}