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Merge "ipq806x: enabled dcache support"

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Linux Build Service Account 2018-03-21 13:01:07 -07:00 • committed by Gerrit - the friendly Code Review server
commit 76e2fcb6b3
4 changed files with 21 additions and 3 deletions
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4
board/qca/arm/common/board_init.c
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@ -343,12 +343,12 @@ void report_l2err(u32 l2esr)
}
#endif
void enable_caches(void)
__weak void enable_caches(void)
{
icache_enable();
}
void disable_caches(void)
__weak void disable_caches(void)
{
icache_disable();
}

12
board/qca/arm/ipq806x/ipq806x.c
View file

@ -968,3 +968,15 @@ void clear_l2cache_err(void)
set_l2_indirect_reg(L2ESR_IND_ADDR, val);
#endif
}
void enable_caches(void)
{
icache_enable();
dcache_enable();
}
void disable_caches(void)
{
icache_disable();
dcache_disable();
}

6
drivers/mmc/mmc.c
View file

@ -385,6 +385,11 @@ static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
if (err)
return err;
mmc->ocr = cmd.response[0];
/*1ms delay is added to give cards time to respond*/
if(!use_arg)
udelay(1000);
return 0;
}
@ -416,6 +421,7 @@ static int mmc_complete_op_cond(struct mmc *mmc)
uint start;
int err;
udelay(100);
mmc->op_cond_pending = 0;
if (!(mmc->ocr & OCR_BUSY)) {
start = get_timer(0);

2
include/configs/ipq806x.h
View file

@ -334,7 +334,7 @@ typedef struct {
* Cache flush and invalidation based on L1 cache, so the cache line
* size is configured to 64 */
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_DCACHE_OFF
/*#define CONFIG_SYS_DCACHE_OFF*/
/* Enabling this flag will report any L2 errors.
* By default we are disabling it */