This patch fixes the erase timeout issue in emmc.
Change-Id: I35031d834fda4ee7560e84787e18e8bc0a3f28fe
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
This command helps to debug the phy issues.
Change-Id: If8354d6826795d9ef9d44112582d3b911963bda5
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
This patch fixes the issues in below i2c commands.
i2c probe , i2c md and i2c mw commands.
Change-Id: I3dd99e8846452b20a71b0664d325b309f3564579
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
This patch enables SPI-NAND support for DK and making
chip select gpio configurable from DTS.
Change-Id: I2ca7d3021fa27da1d83e2a787a1dc626919124f8
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Enabling spi dma driver for ipq40xx. This patch
also enables rx and tx pipe configurable from dts.
Change-Id: Id6009f6e9863ab2cdf8b105461d62aa68e3d004b
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Enable the PPE tx_mac only if the phy link is up else disble
the PPE tx_mac.
Change-Id: I7226a104fa287f8378b98923a00d0caa3f91079d
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
This is a snapshot of the spi_nand as of uboot-1.0
commit:
e6434d80905a219860c8ede78377221ded2510f2 (ipq40xx:
Add bit-flip threshold for QPIC NAND)
Change-Id: I91db5822cc450e9d7eb52fca9eab213784547206
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
1. This driver is directly being registered with MTD
layer.So for OOB operations, the device OOB size will be
passed. NAND controller can’t handle the complete OOB so
calculate NAND Controller supported OOB size and overwrite
the device OOB size with that.
2. Enabling 8 bit ECC support in dev0_ecc_cfg register
Change-Id: I5f4297932eea6bed47182d235d081cbe30d1b85c
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
using nand command will change the default nand device to 1. This will
try to read the nor patitions so one if user tries to read the nand partitions.
Change-Id: Id73e89f479b5735fd5b28a871680190f48a76f0e
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
The erase timeout has been calculated using the
EXT_CSD_TRIM_MULT so that the erase operation with
larger block counts are not affected.
Change-Id: Ia6dd9318c44b4da315c2b2a82cfabe9eff0aeb41
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
As DK and AK does not have pci-phy entry making it as
applicable only for HK
Change-Id: I52d110f4012b867bb019859be9168b3aea68bfd4
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
SGMII channel 0 is used for uniphy instance 1 and 2,
so set the SG_MODE for uniphy instance 1 and 2. Channel 0,1
and 4 are used for instance 0. So set CH1_CH0_SGMII and
CH4_CH1_0_SGMII for channel 1 and 4 respectively.
Change-Id: Ie6f0afa6419a9895f730c89fa27fb80b122acf73
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
This patch enables SDHCI mode and also supports
data transfer using ADMA method.
Change-Id: Ia3187fec9024ad0972ca720cf0b9ddc6a59b906c
Signed-off-by: Vasudevan Murugesan <vmuruges@codeaurora.org>
Reset command must be the first command issued to all
targets after the NAND flash device is powered on.
Change-Id: I617dc5b0ad8d72705dcf20f1cb554134b166e533
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
MDIO clock divider is set to 0x7 (counts to 8)
to produce 12.5MHz (100MHz/8) MDC frequency.
Change-Id: Ic7969aebf9fcbb14601ba8e56563959ab0b25657
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
The EDMA HW is unable to process packets less than MIN_PKT_SIZE(33) bytes,
then the EDMA stalls. This is to pad the packets up to MIN_PKT_SIZE.
Change-Id: I473831a759ad6a764fefa095cf7ab347ba95ee97
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
