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ipq807x: Add QSGMII mode support

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Change-Id: Ic952513f482590a66341d88606ad7da5d2c405a7
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
This commit is contained in:
Sham Muthayyan 2017-11-21 18:46:20 +05:30
parent 692b869ea1
commit e4217213f7
8 changed files with 93 additions and 15 deletions
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2
arch/arm/dts/ipq807x-hk01-c2.dts
View file

@ -28,7 +28,7 @@
pci1 = "/pci@10000000";
};
ess-switch {
switch_mac_mode = <0x0>;
switch_mac_mode = <0x5>;
switch_mac_mode1 = <0xFF>;
switch_mac_mode2 = <0x2>;
aquantia_port = <5>;

22
drivers/net/ipq807x/ipq807x_edma.c
View file

@ -55,6 +55,8 @@ extern int ipq_mdio_read(int mii_id,
int regnum, ushort *data);
extern void ipq_qca8075_phy_map_ops(struct phy_ops **ops);
extern int ipq_qca8075_phy_init(struct phy_ops **ops);
extern void qca8075_phy_interface_set_mode(uint32_t phy_id,
uint32_t mode);
extern int ipq_qca8033_phy_init(struct phy_ops **ops, u32 phy_id);
extern int ipq_qca_aquantia_phy_init(struct phy_ops **ops, u32 phy_id);
@ -1605,6 +1607,7 @@ int ipq807x_edma_init(void *edma_board_cfg)
ipq807x_edma_board_cfg_t ledma_cfg, *edma_cfg;
static int sw_init_done = 0;
int port_8033 = -1, node, phy_addr, aquantia_port = -1;
int mode;
node = fdt_path_offset(gd->fdt_blob, "/ess-switch");
if (node >= 0)
@ -1613,6 +1616,12 @@ int ipq807x_edma_init(void *edma_board_cfg)
if (node >= 0)
aquantia_port = fdtdec_get_uint(gd->fdt_blob, node, "aquantia_port", -1);
mode = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode", -1);
if (mode < 0) {
printf("Error: switch_mac_mode not specified in dts");
return;
}
memset(c_info, 0, (sizeof(c_info) * IPQ807X_EDMA_DEV));
memset(enet_addr, 0, sizeof(enet_addr));
memset(&ledma_cfg, 0, sizeof(ledma_cfg));
@ -1717,13 +1726,18 @@ int ipq807x_edma_init(void *edma_board_cfg)
if (ipq_qca8075_phy_init(&ipq807x_edma_dev[i]->ops[phy_id]) == 0) {
sw_init_done = 1;
}
} else {
} else {
ipq_qca8075_phy_map_ops(&ipq807x_edma_dev[i]->ops[phy_id]);
}
break;
}
if (mode == PORT_WRAPPER_PSGMII)
qca8075_phy_interface_set_mode(0x0, 0x0);
else if ( mode == PORT_WRAPPER_QSGMII)
qca8075_phy_interface_set_mode(0x0, 0x4);
break;
case QCA8033_PHY:
ipq_qca8033_phy_init(&ipq807x_edma_dev[i]->ops[phy_id], phy_addr);
break;
break;
case AQUANTIA_PHY_107:
case AQUANTIA_PHY_109:
case AQUANTIA_PHY_111:

5
drivers/net/ipq807x/ipq807x_ppe.c
View file

@ -21,6 +21,7 @@
#include "ipq807x_ppe.h"
#include "ipq807x_uniphy.h"
#include <fdtdec.h>
#include "ipq_phy.h"
DECLARE_GLOBAL_DATA_PTR;
#define pr_info(fmt, args...) printf(fmt, ##args);
@ -1051,9 +1052,9 @@ void ipq807x_ppe_interface_mode_init(void)
return;
}
mode0 = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode0", -1);
mode0 = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode", -1);
if (mode0 < 0) {
printf("Error: switch_mac_mode0 not specified in dts");
printf("Error: switch_mac_mode not specified in dts");
return;
}

12
drivers/net/ipq807x/ipq807x_uniphy.c
View file

@ -22,6 +22,7 @@
#include <asm/arch-ipq807x/edma_regs.h>
#include "ipq807x_edma.h"
#include "ipq807x_uniphy.h"
#include "ipq_phy.h"
extern int ipq_mdio_write(int mii_id,
int regnum, u16 value);
@ -111,6 +112,14 @@ static void ppe_uniphy_psgmii_mode_set(uint32_t uniphy_index)
ppe_gcc_uniphy_soft_reset(uniphy_index);
}
static void ppe_uniphy_qsgmii_mode_set(uint32_t uniphy_index)
{
ppe_gcc_uniphy_xpcs_reset(uniphy_index, true);
writel(0x120, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ PPE_UNIPHY_MODE_CONTROL);
ppe_gcc_uniphy_soft_reset(uniphy_index);
}
static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t channel)
{
uint32_t reg_value;
@ -196,6 +205,9 @@ void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode)
case PORT_WRAPPER_PSGMII:
ppe_uniphy_psgmii_mode_set(uniphy_index);
break;
case PORT_WRAPPER_QSGMII:
ppe_uniphy_qsgmii_mode_set(uniphy_index);
break;
case PORT_WRAPPER_SGMII0_RGMII4:
ppe_uniphy_sgmii_mode_set(uniphy_index, 0);
break;

8
drivers/net/ipq807x/ipq807x_uniphy.h
View file

@ -15,14 +15,6 @@
#define PPE_UNIPHY_INSTANCE1 1
#define PPE_UNIPHY_INSTANCE2 2
enum port_wrapper_cfg {
PORT_WRAPPER_PSGMII = 0,
PORT_WRAPPER_SGMII0_RGMII4,
PORT_WRAPPER_USXGMII,
PORT_WRAPPER_SGMII1_RGMII4,
PORT_WRAPPER_SGMII4_RGMII4,
};
#define GCC_UNIPHY0_MISC 0x01856004
#define GCC_UNIPHY_REG_INC 0x100
#define GCC_UNIPHY_USXGMII_XPCS_RESET 0x4

10
drivers/net/ipq_common/ipq_phy.h
View file

@ -82,6 +82,16 @@ typedef enum {
FAL_CABLE_STATUS_BUTT = 0xffff,
} fal_cable_status_t;
enum port_wrapper_cfg {
PORT_WRAPPER_PSGMII = 0,
PORT_WRAPPER_SGMII0_RGMII4,
PORT_WRAPPER_USXGMII,
PORT_WRAPPER_SGMII1_RGMII4,
PORT_WRAPPER_SGMII4_RGMII4,
PORT_WRAPPER_QSGMII,
};
struct phy_ops {
u8 (*phy_get_link_status) (u32 dev_id, u32 phy_id);
u32 (*phy_get_duplex) (u32 dev_id, u32 phy_id,

43
drivers/net/ipq_common/ipq_qca8075.c
View file

@ -734,6 +734,49 @@ void ipq_qca8075_phy_map_ops(struct phy_ops **ops)
*ops = qca8075_ops;
}
void qca8075_phy_serdes_reset(u32 phy_id)
{
qca8075_phy_reg_write(0,
phy_id + QCA8075_PHY_PSGMII_ADDR_INC,
QCA8075_MODE_RESET_REG,
QCA8075_MODE_CHANAGE_RESET);
mdelay(100);
qca8075_phy_reg_write(0,
phy_id + QCA8075_PHY_PSGMII_ADDR_INC,
QCA8075_MODE_RESET_REG,
QCA8075_MODE_RESET_DEFAULT_VALUE);
}
static u16 qca8075_phy_interface_get_mode(u32 phy_id)
{
u16 phy_data;
phy_data = qca8075_phy_reg_read(0,
phy_id + QCA8075_PHY_MAX_ADDR_INC,
QCA8075_PHY_CHIP_CONFIG);
phy_data &= 0x000f;
return phy_data;
}
void qca8075_phy_interface_set_mode(u32 phy_id, u32 mode)
{
u16 phy_data;
phy_data = qca8075_phy_interface_get_mode(phy_id);
if (phy_data != mode) {
phy_data = qca8075_phy_reg_read(0,
phy_id + QCA8075_PHY_MAX_ADDR_INC,
QCA8075_PHY_CHIP_CONFIG);
phy_data &= 0xfff0;
qca8075_phy_reg_write(0,
phy_id + QCA8075_PHY_MAX_ADDR_INC,
QCA8075_PHY_CHIP_CONFIG,
phy_data | mode);
qca8075_phy_serdes_reset(0);
}
}
int ipq_qca8075_phy_init(struct phy_ops **ops)
{
u16 phy_data;

6
drivers/net/ipq_common/ipq_qca8075.h
View file

@ -63,6 +63,12 @@
#define QCA8075_PHY4_AUTO_BX1000_SELECT 0x10
#define QCA8075_PHY4_AUTO_FX100_SELECT 0x8
#define QCA8075_MODE_RESET_REG 0x0
#define QCA8075_MODE_CHANAGE_RESET 0x0
#define QCA8075_MODE_RESET_DEFAULT_VALUE 0x5f
#define QCA8075_PHY_MAX_ADDR_INC 0x4
#define QCA8075_PHY_PSGMII_ADDR_INC 0x5
#define QCA8075_PHY_CHIP_CONFIG 0x1f /* Chip Configuration Register */
#define BT_BX_SG_REG_SELECT BIT_15
#define BT_BX_SG_REG_SELECT_OFFSET 15