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ipq807x: SGMII mode settings for all the channels

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SGMII channel 0 is used for uniphy instance 1 and 2,
so set the SG_MODE for uniphy instance 1 and 2. Channel 0,1
and 4 are used for instance 0. So set CH1_CH0_SGMII and
CH4_CH1_0_SGMII for channel 1 and 4 respectively.

Change-Id: Ie6f0afa6419a9895f730c89fa27fb80b122acf73
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
This commit is contained in:
Sham Muthayyan 2017-11-08 11:20:55 +05:30 • committed by Gerrit - the friendly Code Review server
parent 6a215d32ad
commit f3af149d5f
2 changed files with 27 additions and 3 deletions
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25
drivers/net/ipq807x/ipq807x_uniphy.c
View file

@ -111,8 +111,10 @@ static void ppe_uniphy_psgmii_mode_set(uint32_t uniphy_index)
ppe_gcc_uniphy_soft_reset(uniphy_index);
}
static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index)
static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index, uint32_t channel)
{
uint32_t reg_value;
writel(UNIPHY_MISC2_REG_SGMII_MODE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_MISC2_REG_OFFSET);
writel(UNIPHY_PLL_RESET_REG_VALUE, PPE_UNIPHY_BASE +
@ -121,7 +123,18 @@ static void ppe_uniphy_sgmii_mode_set(uint32_t uniphy_index)
writel(UNIPHY_PLL_RESET_REG_DEFAULT_VALUE, PPE_UNIPHY_BASE +
(uniphy_index * PPE_UNIPHY_REG_INC) + UNIPHY_PLL_RESET_REG_OFFSET);
ppe_gcc_uniphy_xpcs_reset(uniphy_index, true);
writel(0x420, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
reg_value = readl( PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ PPE_UNIPHY_MODE_CONTROL);
if (uniphy_index == PPE_UNIPHY_INSTANCE0) {
if (channel == 1)
reg_value |= UNIPHY_CH1_CH0_SGMII;
else if (channel == 4)
reg_value |= UNIPHY_CH4_CH1_0_SGMII;
} else {
reg_value |= UNIPHY_SG_MODE;
}
writel(reg_value, PPE_UNIPHY_BASE + (uniphy_index * PPE_UNIPHY_REG_INC)
+ PPE_UNIPHY_MODE_CONTROL);
ppe_gcc_uniphy_soft_reset(uniphy_index);
}
@ -184,7 +197,13 @@ void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode)
ppe_uniphy_psgmii_mode_set(uniphy_index);
break;
case PORT_WRAPPER_SGMII0_RGMII4:
ppe_uniphy_sgmii_mode_set(uniphy_index);
ppe_uniphy_sgmii_mode_set(uniphy_index, 0);
break;
case PORT_WRAPPER_SGMII1_RGMII4:
ppe_uniphy_sgmii_mode_set(uniphy_index, 1);
break;
case PORT_WRAPPER_SGMII4_RGMII4:
ppe_uniphy_sgmii_mode_set(uniphy_index, 4);
break;
case PORT_WRAPPER_USXGMII:
ppe_uniphy_usxgmii_mode_set(uniphy_index);

5
drivers/net/ipq807x/ipq807x_uniphy.h
View file

@ -19,6 +19,8 @@ enum port_wrapper_cfg {
PORT_WRAPPER_PSGMII = 0,
PORT_WRAPPER_SGMII0_RGMII4,
PORT_WRAPPER_USXGMII,
PORT_WRAPPER_SGMII1_RGMII4,
PORT_WRAPPER_SGMII4_RGMII4,
};
#define GCC_UNIPHY0_MISC 0x01856004
@ -35,6 +37,9 @@ enum port_wrapper_cfg {
#define PPE_UNIPHY_BASE 0X07A00000
#define PPE_UNIPHY_REG_INC 0x10000
#define PPE_UNIPHY_MODE_CONTROL 0x46C
#define UNIPHY_SG_MODE 0x400
#define UNIPHY_CH4_CH1_0_SGMII 0x4
#define UNIPHY_CH1_CH0_SGMII 0x2
#define UNIPHY_MISC2_REG_OFFSET 0x218
#define UNIPHY_MISC2_REG_SGMII_MODE 0x30