This changes enable nor enviornemnt support if its no flash with
eMMC and NAND is disabled.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I1ff389ed388fb7f72543cc87e852c360a965db48
This changes update the TLV offset as per the kernel tlv crash region.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I27d79d5f2d35c4b584292410ee76d26b123d301f
This changes support config based single itb to load kernel
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I163d1788e2875fa8f4dcacb3c1c241535c8658b9
We had identical device-tree for different RDPs
though they are the same except for machid.
This change enables reuse of a single device-tree
across RDPs with same configurations.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Change-Id: If81b431e4a6afe54e427fe0a52de275fdd29df00
This change fixes setting dirty bit in CMD_RCGR and configure GMAC
to run on GPLL4 clock source.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I01bb0e3af2da93f0464d41a6bd571480b1a4e581
Update usb controller and phy
configuration for enumeration.
Signed-off-by: Manikanta Mylavarapu <mmanikan@codeaurora.org>
Change-Id: I9e20fe5bf4c7abe7547f383ab58bff9b8dad64e0
This change will modify PULL value for eMMC CMD line.
with this change the pull value will be GPIO_PULL_UP.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: Id884ef4742dca5f2f30c699aa2ab48c0d3c7cc97
This change will fix serial training logic and enable
config to enable default qpic_io_macro clock @ 80MHz with
default phase delay valu 4 for all qspi serial line.
This change also fix the delay issue while writing to qpic
register via bam.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I345f736fdae9d48b6da0115ca7a8519b43fe9efd
This Gephy is internal phy driver for ethernet
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ia4e744c0fbd990bdc94fe93263ac2ddbe4cecf61
This changes remove emulation dts and add mp02.1 dts support in
Makefile for tiny-nor build
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I99d28415442b4079d4e67e586b794b88aba403a2
Remove support for hk05 since it is
marked as obsolete in default setting table
Signed-off-by: Karthick Shanmugham <kartshan@codeaurora.org>
Change-Id: I972af09f912c1f613b462cf2559d8a645a0bb270
This is missing, with causes lldiv() to fail on boards with use the private
libgcc. Add the missing routine.
Code is available for using the CLZ instruction but it is not enabled at
present.
This comes from coreboot version 4.0.
Signed-off-by: Simon Glass <sjg@chromium.org>
(cherry picked from commit 9ab60493c9)
Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org>
Change-Id: Id1d604819be2a98e1cc1ea306902a86323135679
This config need not be defined for IPQ806x. U-boot in
IPQ806x, can run without this CP15BEN setting.
Change-Id: I1b95e2a06f72dcc763a885f81b591d7d529dd446
Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org>
This change will remove GCC_SDCC1_MISC register from
SDCC clock configuration code path. Since in ipq5018 this
register is not available. so removining this register.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I980fc0f0ce24cd0da5610300608a5dd223c33941
This change will add support to write some ops group register via
BAM to avoid xPU error.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I65ea875f783b7254f01cb3cf43eb43295caa4ed9
This changes remove double calculation of N and D values.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I1c8444b5f6dbbc06a2b676477599978d6a91a681
This change is to remove SBL and U-Boot reserved memory nodes
in crashdump disabled case.
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Change-Id: Iea9d7e483e2766ec6124c9ec833dd81c3c8e9046
In fig branch, 4k nand HLOS images are not generated yet.
In pack script, we are generating nand-4k and norplusnand-4k
images if nand and norplusnand flash type is selected.
So, added an option "--skip_4k_nand" to skip generating
4k nand single images.
Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org>
Change-Id: I487c3e7d150a7165a70e2a4e1c13581eeaa08bb1
This changes initialize clock and enable the block of
Gephy, Uniphy, GMAC0 & GMAC1 and also udpate Rx & Tx clock
based on speed.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ia2627e17f7029c2d0d1cbb9eff26afb27aa1c057
This changes avoid initialize the usb if not present in dts.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I8d5666f1cceedb47b121ce6aefae93aa8c64d130
This changes remove soc dtsi header file and
add only uart and timer nodes.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I87c1f7c87514e993fed7cd4ff14920309d5eb9b3
This change will add support for serial training in
QPIC.
Due to different PNR and PCB delays, serial read data
can come with different delays to QPIC. At high frequency
operations Rx clock should be adjusted according to delays
so that Rx Data can be captured correctly. CLK_CNTR_INIT_VAL_VEC
in NAND_FLASH_SPI_CFG register is a 12-bit vector which is divided
in 4 parts of 3 bits each representing delay of 4 serial input data
lines. Bit [2:0] corresponds to qspi_miso[0], bit [5:3] corresponds
to qspi_miso[1], bit [8:6] corresponds to qspi_miso[2] and bit [11:9]
corresponds to qspi_miso[3]. Delay of each qspi_miso line can be set
from 0 to 7.
For serial training the following rule should be followd.
1) SW should write a page with any known pattern in flash at lower
frequency.
2) Set the CLK_CNTR_INIT_VAL_VEC for qspi_miso[0] line.
3) Read that page repetitively in high frequency mode until it
gets data accurately.
4) Repeat above steps for other qspi_miso lines.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: If622809efff55fb2abe60f409a590abd5313741b
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This change duplicate the mp03.1 dts with minimal node.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I90a7eac51f022af0d66865cbe6b4df6bc57972a7
