Adding support for DK04-C2,C3,C4,C5 and
DK07-C1,C2,C3 boards.
Change-Id: I2727645086328331deffd63849bedbf119d163c8
Signed-off-by: Sasirekaa Madhesu <smadhesu@codeaurora.org>
Enabling spi dma driver for ipq40xx. This patch
also enables rx and tx pipe configurable from dts.
Change-Id: Id6009f6e9863ab2cdf8b105461d62aa68e3d004b
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Added check for dcache status before flushing.
Change-Id: I69462aa7852f96611e663acdf43aecd005a50c38
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
If crashdump magic is found, should not allow user
to access u-boot prompt as tz will be in unsecure state.
Change-Id: I081e84eceada7ffe72d9b4fa4f0425535e4aabde
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Print spi 3 byte address by default if the
SMEM_SPI_FLASH_ADDR_LEN ID is not passed in smem.
Change-Id: I6b55401adb89a1341130465ae307c30901ce7895
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
This patch enables SDHCI mode and also supports
data transfer using ADMA method.
Change-Id: Ia3187fec9024ad0972ca720cf0b9ddc6a59b906c
Signed-off-by: Vasudevan Murugesan <vmuruges@codeaurora.org>
Reset command must be the first command issued to all
targets after the NAND flash device is powered on.
Change-Id: I617dc5b0ad8d72705dcf20f1cb554134b166e533
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
This SMEM type is to determine the spi flash addr is in 3 byte
or 4 byte.
Change-Id: I705a9c5c6f760b93e112a873ead41cd76520501b
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Added a separate dumpinfo entry for
Secure boot to skip secure region.
Change-Id: Ib3836a851e8b0603a9c08013de293dcbe8e3c0fb
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
NSS-IMEM region is copied to a dynamic address
region in DRAM during kernel crash to avoid
NSS dump corruption.
This patch includes support to save the NSS dump
from the dynamic DRAM region to file in host machine.
Change-Id: I6131da890dc8bde382a3d2511ea930cd76c1f79e
Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
A processor can execute instructions from a memory
region only if the access permissions for its
current state permit read access, and the XN
bit is set to 0.
The domain access is to be set as "clients"
for proper functioning of XN bit.
Change-Id: I86daffa828fa7b2fa365e358ef7042630ab98d60
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Updated number of alternate partitions and
alternate partition data structure to match
smem entry.
Change-Id: I62484e369ed3d35037237fde2d71f9af045e438a
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
get_ticks() will return the timer counter value.
get_tbclk() will return the timer frequency.
Change-Id: Ib698f1c1d58403ae22381b6de8c6518beb4c34cf
Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
Added scm_call wrapper to support fuseipq
command to work with 64 bit scm_call.
Change-Id: Ie1fd2925e9f7ed5b3eb57eb44b1c360d0d7de916
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Added device tree to support for HK05 and HK06 boards
based on ipq807x SoC.
Change-Id: I78a49340cbfc6c4f6c4ee5a3171cc1b6dd6ad1ed
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
The QPIC XFER STEPS will not be configured in non NAND boot
mode and the data transfer speed will be very slow. Now this
patch reads the timing parameter from ONFI page and configures
the NAND XFER STEPS registers for highest supported ONFI mode.
For NON ONFI device, it will configure to default mode.
Change-Id: I2daf4a92255307efc53db9bb7fe2f02e8c00c3fa
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Added individual device trees for DB.HK01 and DB.HK02
boards to manage their configurations individually.
Change-Id: I5846b08a11febd5e7559b08b558245dc4f75c70e
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
