mirror/u-boot-2016
1
0
Fork 0
mirror of https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git synced 2026-03-14 21:10:27 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

ARM:cache-cp15: Set Domain Access Control Register

Browse source 
A processor can execute instructions from a memory
region only if the access permissions for its
current state permit read access, and the XN
bit is set to 0.

The domain access is to be set as "clients"
for proper functioning of XN bit.

Change-Id: I86daffa828fa7b2fa365e358ef7042630ab98d60
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
This commit is contained in:
Gokul Sriram Palanisamy 2017-08-22 13:37:53 +05:30 • committed by Gerrit - the friendly Code Review server
parent 9dc890a648
commit fd0bc4b933
1 changed files with 51 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

51
arch/arm/lib/cache-cp15.c
View file

@ -62,6 +62,56 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
}
#if defined(CONFIG_ARCH_IPQ40xx) || defined(CONFIG_ARCH_IPQ807x)
#define UBOOT_CACHE_SETUP 0x100e
#define GEN_CACHE_SETUP 0x101e
__weak void dram_bank_mmu_setup(int bank)
{
bd_t *bd = gd->bd;
int i;
debug("%s: bank: %d\n", __func__, bank);
for (i = bd->bi_dram[bank].start >> 20;
i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
i++) {
/* Set XN bit for all dram regions except uboot code region */
if (i >= (CONFIG_SYS_TEXT_BASE >> 20) && i < ((CONFIG_SYS_TEXT_BASE + 0x100000) >> 20))
set_section_dcache(i, UBOOT_CACHE_SETUP);
else
set_section_dcache(i, GEN_CACHE_SETUP);
}
}
/* to activate the MMU we need to set up virtual memory: use 1M areas */
static inline void mmu_setup(void)
{
int i;
u32 reg;
arm_init_before_mmu();
/* Set up an identity-mapping for all 4GB, rw for everyone */
for (i = 0; i < 4096; i++)
set_section_dcache(i, DCACHE_WRITEALLOC);
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
dram_bank_mmu_setup(i);
}
/* Copy the page table address to cp15 */
asm volatile("mcr p15, 0, %0, c2, c0, 0"
: : "r" (gd->arch.tlb_addr) : "memory");
/* Set the access control to all clients */
set_dacr(0x55555555);
/* and enable the mmu */
reg = get_cr(); /* get control reg. */
cp_delay();
set_cr(reg | CR_M);
}
#else
__weak void dram_bank_mmu_setup(int bank)
{
bd_t *bd = gd->bd;
@ -124,6 +174,7 @@ static inline void mmu_setup(void)
cp_delay();
set_cr(reg | CR_M);
}
#endif
static int mmu_enabled(void)
{