This patch updates the following:
1) Removes unused/duplicate macro: NSS_CC_PORT1_RX_CBCR_ADDR
2) Remove CMN_BLK_INIT
3) Update MAX Ports to 6
4) Rename switch_mac_mode to switch_mac_mode0 in DTS and driver
5) Fix SYSNOC frequency configuration
6) Tx/Rx descs is initialized to 0 before use which is
needed because Alder DDR is not init to 0 by default.
Change-Id: Ide22e146f9c8ecb75585d0a8d04e426c463ad8c9
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
This changes add pci 2 lane support in pci driver
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ia4235c277e91d68366f6ae8aa16d8505a2ca5b05
This patch updates the following:
1) Update speed clock, port mac clock reset for ipq9574
platform.
2) Handle PPE init for all 3 switch mac modes.
3) Handle port mux config when port5 is part of Uniphy0
during when Uniphy1 won't be used.
Change-Id: I23b04b00036ab139cd5877bcf913dbecb7fb7fa2
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
This patch updates the following:
1) Add support for 3 switch_mac_modes in ipq9574 platform.
2) Update xpcs and soft_reset as needed for ipq9574 platform.
3) Support usecase where 5*1G ports can be supported as part
of Uniphy0 during when Uniphy1 won't be used.
Change-Id: I949db117fa3c8adb937c5c055eedcaa6ead0da07
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
This patch updates the following:
1) Handle 2 aquantia ports during ping
2) Remove SFP Port Support Temporarily
3) Update clocks for different port speeds and different
ethernet port types as needed.
4) Update number of ports to 7 since 7 is the MAX ports
supported in ipq9574 platform.
Change-Id: I2d9040227b9c8a11cddc0d00e835ac64d3a4940d
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
This change will add support for 4K Macronix spi nand
"MX35UF4GE4AD-Z4I"
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Change-Id: I94e07d9e25de46c67fcb679ef149990e093afc8f
This patch moves the entire Uniphy configurations to
!CONFIG_IPQ9574_RUMI as there is no PHY/UNIPHY in EMU
Platform.
Change-Id: I404916d10caed87e4825172345195bf92df1b725
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
This patch updates the VSI settings. The VSI Table size has
now changes from 3 word to 4 word and the same has been
accomodated. Without writing 4 words to that Table, the VSI
writes won't be processed by the H/W.
This patch updates the scheduling, TDM configuration
and the ppe port mux configuration as required for ipq95xx.
This patch also moves the configurations not required
for EMU Platform to !CONFIG_IPQ9574_RUMI.
Change-Id: Id54e40d26e80c36e7a61642d8494c30bbd3ea2a5
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
This patch updates the address of the EDMA registers, removes
registers which are not used and then does the required changes
to accomodate the new EDMA Descriptor format.
This patch also does the required changes to accomodate Secondary
Descriptor which is added instead of preheaders in ipq95xx.
We have also updated the number of descriptors per ring to 128
with this patch and have also moved the configs not required for
EMU Platform to !CONFIG_IPQ9574_RUMI.
Change-Id: I6e98c457d76c66f87b74cc0eafa7088d0081f533
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
This change will add support for Macronix "MX35UF1GE4AC" spi nand
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I66e82e22217d655b44e30baa64f3aefd5a5f2aaa
This change will add support for winbond "W25N02JWZEIF"
spi nand device.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I1dd258c3f0f3174d09e74fb7ffd0c26a43e6c24b
This change will add support for giga device GD5F1GQ5REYIG
spi nand support.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I57211ce34543de81216d86653a45519b97cf2fb0
Added config, dts and initial board support code for ipq9048.
Signed-off-by: anusha <anusharao@codeaurora.org>
Change-Id: Ib4d0da9aedd5c98b02c59dd83d9efa78baada335
This change will change serial training data read to one complete
page instead of 64-bytes read. Partial page read will cause some
data curroption issue if read request failed so read one complete page.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: Ibad101f096440e5dc10dfb4b3329a0aa6bddee7d
This change will fix proper clock source macro in set_clk_rate function.
Currently we are passing the wrong value to qpic_set_clk_rate for clock
source.
wrong:
qpic_set_clk_rate(IO_MACRO_CLK_200_MHZ, QPIC_IO_MACRO_CLK, NAND_QSPI_MSTR_CONFIG);
The last argument should be clock source not register base address.
correct:
qpic_set_clk_rate(IO_MACRO_CLK_200_MHZ, QPIC_IO_MACRO_CLK, GPLL0_CLK_SRC);
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: Ie9e07c253220924fd0c9287f7f0e2c5d42351128
After reading data from mmc, dest pointer will point to
the end address. To calculate the start of dest pointer
number of bytes copied has to be subtracted.
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Change-Id: I24610a3b3bb498c4ee4ebba58e557d109c6af1ef
After reading data from mmc, dest pointer will point to
the end address. To calculate the start of dest pointer
number of bytes copied has to be subtracted.
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Change-Id: I24610a3b3bb498c4ee4ebba58e557d109c6af1ef
This change will fix memory leak problem in serial training.
For serial tarining we are allocating memory to hold the training
pattern buf. For any failure we are freeing the buffer but due to
wrong lavel used memory was not getting freed due to this memory leak
problem is happening.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Change-Id: I35ffd27df9b24ea53aed9e9f0623d8890ba66f06
This change make the qca_8337 switch initialization generic based on
dts irrespective of gmac controller.
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: I292992307ead2cd7bbb0763ff483dc16c266d417
This change fix Access violation created by APPS
master by accessing QPIC_XPU issue due to accessing
QPIC_QSPI_MSTR_CONFIG & QPIC_NAND_FLASH_SPI_CFG registers
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Change-Id: Ibb840db12359eea01823dd7732fcb1ac1e7b8967
