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drivers: net: ipq9574: Update PPE Driver

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This patch updates the VSI settings. The VSI Table size has
now changes from 3 word to 4 word and the same has been
accomodated. Without writing 4 words to that Table, the VSI
writes won't be processed by the H/W.

This patch updates the scheduling, TDM configuration
and the ppe port mux configuration as required for ipq95xx.

This patch also moves the configurations not required
for EMU Platform to !CONFIG_IPQ9574_RUMI.

Change-Id: Id54e40d26e80c36e7a61642d8494c30bbd3ea2a5
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
This commit is contained in:
Selvam Sathappan Periakaruppan 2021-05-13 17:24:20 +05:30 • committed by Gerrit - the friendly Code Review server
parent 48298857ba
commit 4db507bac7
3 changed files with 379 additions and 820 deletions
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1108
drivers/net/ipq9574/ipq9574_ppe.c
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File diff suppressed because it is too large Load diff

64
drivers/net/ipq9574/ipq9574_ppe.h
View file

@ -25,26 +25,44 @@
#include <net.h>
#include <miiphy.h>
#define GCC_NSS_PORT1_RX_CMD_RCGR 0x01868020
#define GCC_NSS_PORT1_RX_CFG_RCGR 0x01868024
#define NSS_CC_PORT1_RX_CMD_RCGR 0x39B28110
#define NSS_CC_PORT1_RX_CFG_RCGR 0x39B28114
#define GCC_NSS_PORT1_RX_MISC 0x01868400
#define IPQ9574_PPE_BASE_ADDR 0x3a000000
#define IPQ9574_PPE_REG_SIZE 0x1000000
#define PORT1 1
#define PORT2 2
#define PORT3 3
#define PORT4 4
#define PORT5 5
#define PORT6 6
#define IPQ9574_PORT5_MUX_PCS_UNIPHY0 0x0
#define IPQ9574_PORT5_MUX_PCS_UNIPHY1 0x1
#define PORT_GMAC_TYPE 1
#define PORT_XGMAC_TYPE 2
#define IPQ9574_PORT_MUX_MAC_TYPE 0
#define IPQ9574_PORT_MUX_XMAC_TYPE 1
struct port_mux_ctrl {
uint32_t port3_pcs_sel:2;
uint32_t port4_pcs_sel:2;
uint32_t port5_pcs_sel:2;
uint32_t port5_gmac_sel:1;
uint32_t pcs0_ch4_sel:1;
uint32_t pcs0_ch0_sel:1;
uint32_t _reserved0:23;
uint32_t port1_pcs_sel:1;
uint32_t port2_pcs_sel:1;
uint32_t port3_pcs_sel:1;
uint32_t port4_pcs_sel:1;
uint32_t port5_pcs_sel:1;
uint32_t port6_pcs_sel:1;
uint32_t _reserved0:2;
uint32_t port1_mac_sel:1;
uint32_t port2_mac_sel:1;
uint32_t port3_mac_sel:1;
uint32_t port4_mac_sel:1;
uint32_t port5_mac_sel:1;
uint32_t port6_mac_sel:1;
uint32_t _reserved1:18;
};
union port_mux_ctrl_u {
@ -108,25 +126,15 @@ union ipo_action_u {
};
#define IPQ9574_PORT_MUX_CTRL 0x10
#define CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2 0
#define CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4 1
#define CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3 0
#define CPPE_PORT4_PCS_SEL_PCS0_SGMIIPLUS 1
#define CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4 0
#define CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0 1
#define CPPE_PORT5_GMAC_SEL_GMAC 0
#define CPPE_PORT5_GMAC_SEL_XGMAC 1
#define CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK 0x0
#define CPPE_PCS0_CHANNEL4_SEL_PORT3_CLOCK 0x1
#define CPPE_PCS0_CHANNEL0_SEL_PSGMII 0x0
#define CPPE_PCS0_CHANNEL0_SEL_SGMIIPLUS 0x1
#define CPPE_DETECTION_PHY_FAILURE 0xFFFF
#define IPQ9574_PORT_MUX_CTRL_NUM 1
#define IPQ9574_PORT_MUX_CTRL_INC 0x4
#define IPQ9574_PORT_MUX_CTRL_DEFAULT 0x0
#define PORT_PHY_STATUS_ADDRESS 0x44
#define PORT_PHY_STATUS_PORT5_1_OFFSET 16
#define IPQ9574_PPE_IPE_L3_BASE_ADDR 0x200000
#define IPQ9574_PPE_L3_VP_PORT_TBL_ADDR (IPQ9574_PPE_IPE_L3_BASE_ADDR + 0x1000)
#define IPQ9574_PPE_L3_VP_PORT_TBL_ADDR (IPQ9574_PPE_IPE_L3_BASE_ADDR + 0x4000)
#define IPQ9574_PPE_L3_VP_PORT_TBL_INC 0x10
#define IPQ9574_PPE_QUEUE_MANAGER_BASE_ADDR 0x800000
@ -144,8 +152,14 @@ union ipo_action_u {
#define IPQ9574_PPE_MAC_MIB_CTL 0x001034
#define IPQ9574_PPE_TRAFFIC_MANAGER_BASE_ADDR 0x400000
#define IPQ9574_PPE_TM_SHP_CFG_L0_OFFSET 0x00000030
#define IPQ9574_PPE_TM_SHP_CFG_L1_OFFSET 0x00000034
#define IPQ9574_PPE_TM_SHP_CFG_L0 IPQ9574_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
IPQ9574_PPE_TM_SHP_CFG_L0_OFFSET
#define IPQ9574_PPE_TM_SHP_CFG_L1 IPQ9574_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
IPQ9574_PPE_TM_SHP_CFG_L1_OFFSET
#define IPQ9574_PPE_L0_FLOW_PORT_MAP_TBL_ADDR 0x8000
#define IPQ9574_PPE_L0_FLOW_PORT_MAP_TBL_ADDR 0x10000
#define IPQ9574_PPE_L0_FLOW_PORT_MAP_TBL_INC 0x10
#define IPQ9574_PPE_L0_FLOW_PORT_MAP_TBL (IPQ9574_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
IPQ9574_PPE_L0_FLOW_PORT_MAP_TBL_ADDR)
@ -219,7 +233,7 @@ union ipo_action_u {
#define IPQ9574_PPE_PORT_XGMAC2_BITPOS (1 << IPQ9574_PPE_PORT_XGMAC2)
#define IPQ9574_PPE_PORT_CRYPTO1_BITPOS (1 << IPQ9574_PPE_PORT_CRYPTO1)
#define PPE_SWITCH_NSS_SWITCH_XGMAC0 0x3000
#define PPE_SWITCH_NSS_SWITCH_XGMAC0 0x500000
#define NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION 0x4000
#define USS (1 << 31)
#define SS(i) (i << 29)

27
drivers/net/ipq_common/ipq_phy.h
View file

@ -18,7 +18,7 @@
#include <net.h>
#define PHY_MAX 6
#define IPQ9574_PHY_MAX 5
#define IPQ9574_PHY_MAX 6
#define IPQ6018_PHY_MAX 5
#define MDIO_CTRL_0_REG 0x00090040
#define MDIO_CTRL_0_DIV(x) (x << 0)
@ -88,6 +88,31 @@ typedef enum {
FAL_CABLE_STATUS_BUTT = 0xffff,
} fal_cable_status_t;
enum eport_wrapper_cfg {
EPORT_WRAPPER_PSGMII = 0,
EPORT_WRAPPER_PSGMII_RGMII5,
EPORT_WRAPPER_SGMII0_RGMII5,
EPORT_WRAPPER_SGMII1_RGMII5,
EPORT_WRAPPER_PSGMII_RMII0,
EPORT_WRAPPER_PSGMII_RMII1,
EPORT_WRAPPER_PSGMII_RMII0_RMII1,
EPORT_WRAPPER_PSGMII_RGMII4,
EPORT_WRAPPER_SGMII0_RGMII4,
EPORT_WRAPPER_SGMII1_RGMII4,
EPORT_WRAPPER_SGMII4_RGMII4,
EPORT_WRAPPER_QSGMII,
EPORT_WRAPPER_SGMII_PLUS,
EPORT_WRAPPER_USXGMII,
EPORT_WRAPPER_10GBASE_R,
EPORT_WRAPPER_SGMII_CHANNEL0,
EPORT_WRAPPER_SGMII_CHANNEL1,
EPORT_WRAPPER_SGMII_CHANNEL4,
EPORT_WRAPPER_RGMII,
EPORT_WRAPPER_PSGMII_FIBER,
EPORT_WRAPPER_SGMII_FIBER,
EPORT_WRAPPER_MAX = 0xFF
};
enum port_wrapper_cfg {
PORT_WRAPPER_PSGMII = 0,
PORT_WRAPPER_SGMII0_RGMII4,