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drivers: net: ipq9574: Fix ethernet for RDPs

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This patch updates the following:
1) Removes unused/duplicate macro: NSS_CC_PORT1_RX_CBCR_ADDR
2) Remove CMN_BLK_INIT
3) Update MAX Ports to 6
4) Rename switch_mac_mode to switch_mac_mode0 in DTS and driver
5) Fix SYSNOC frequency configuration
6) Tx/Rx descs is initialized to 0 before use which is
needed because Alder DDR is not init to 0 by default.

Change-Id: Ide22e146f9c8ecb75585d0a8d04e426c463ad8c9
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
This commit is contained in:
Selvam Sathappan Periakaruppan 2021-07-26 19:48:02 +05:30 • committed by Gerrit - the friendly Code Review server
parent eed9d45c6c
commit 31ddb16d89
9 changed files with 18 additions and 25 deletions
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2
arch/arm/dts/ipq9574-al01-c1.dts
View file

@ -158,7 +158,7 @@
};
ess-switch {
switch_mac_mode = <PORT_WRAPPER_PSGMII>;
switch_mac_mode0 = <PORT_WRAPPER_PSGMII>;
switch_mac_mode1 = <PORT_WRAPPER_MAX>; /* Unused */
switch_mac_mode2 = <PORT_WRAPPER_USXGMII>;
qca807x_gpio = <60>;

2
arch/arm/dts/ipq9574-al02-c1.dts
View file

@ -157,7 +157,7 @@
};
ess-switch {
switch_mac_mode = <PORT_WRAPPER_PSGMII>;
switch_mac_mode0 = <PORT_WRAPPER_PSGMII>;
switch_mac_mode1 = <PORT_WRAPPER_USXGMII>;
switch_mac_mode2 = <PORT_WRAPPER_USXGMII>;
aquantia_gpio = <37>;

2
arch/arm/dts/ipq9574-db-al01-c1.dts
View file

@ -158,7 +158,7 @@
};
ess-switch {
switch_mac_mode = <PORT_WRAPPER_PSGMII>;
switch_mac_mode0 = <PORT_WRAPPER_PSGMII>;
switch_mac_mode1 = <PORT_WRAPPER_USXGMII>;
switch_mac_mode2 = <PORT_WRAPPER_SGMII_PLUS>;
qca807x_gpio = <60>;

1
arch/arm/dts/ipq9574-emulation.dts
View file

@ -110,6 +110,5 @@
switch_mac_mode0 = <PORT_WRAPPER_SGMII0_RGMII4>;
switch_mac_mode1 = <PORT_WRAPPER_SGMII0_RGMII4>;
switch_mac_mode2 = <PORT_WRAPPER_SGMII0_RGMII4>;
uniphy0_port5 = <1>;
};
};

18
board/qca/arm/ipq9574/ipq9574.c
View file

@ -735,7 +735,6 @@ void set_function_select_as_mdc_mdio(void)
void eth_clock_enable(void)
{
int reg_val, reg_val1, mode, i;
int gcc_pll_base = 0x0009B780;
int node;
/* Clock init */
@ -773,7 +772,7 @@ void eth_clock_enable(void)
/* SYSNOC frequency 343M */
reg_val = readl(0x182E004 + 4);
reg_val &= ~0x7ff;
writel(reg_val | 206, 0x182E004 + 4);
writel(reg_val | 0x206, 0x182E004 + 4);
/* Update Config */
reg_val = readl(0x182E004);
writel(reg_val | 0x1, 0x182E004);
@ -853,21 +852,6 @@ void eth_clock_enable(void)
writel(0x1, NSS_CC_PORT5_TX_CMD_RCGR);
writel(0x2, NSS_CC_PORT5_TX_CMD_RCGR);
/* CMN BLK init */
reg_val = readl(gcc_pll_base + 4);
/* CMN BLK Mode: INTERNAL_48MHZ */
reg_val = (reg_val&0xfffffdf0) | 0x7;
writel(reg_val, gcc_pll_base + 0x4);
reg_val = readl(gcc_pll_base);
reg_val = reg_val | 0x40;
writel(reg_val, gcc_pll_base);
mdelay(1);
reg_val = reg_val & (~0x40);
writel(reg_val, gcc_pll_base);
mdelay(1);
writel(0xbf, gcc_pll_base);
mdelay(1);
/* Uniphy Port5 clock source set */
reg_val = readl(NSS_CC_PORT_SPEED_DIVIDER + 0x64);
reg_val1 = readl(NSS_CC_PORT_SPEED_DIVIDER + 0x70);

1
board/qca/arm/ipq9574/ipq9574.h
View file

@ -53,7 +53,6 @@
#define GCC_NSSNOC_SNOC_1_CBCR 0x181707C
#define GCC_MEM_NOC_SNOC_AXI_CBCR 0x1819018
#define GCC_IMEM_AXI_CBCR 0x180E004
#define NSS_CC_PORT1_RX_CBCR_ADDR 0x39B281A0
#define NSS_CC_UNIPHY_PORT1_RX_ADDR 0x39B28904
#define NSS_CC_PPE_RESET_ADDR 0x39B28A08
#define NSS_CC_UNIPHY_MISC_RESET 0x39B28A24

13
drivers/net/ipq9574/ipq9574_edma.c
View file

@ -677,6 +677,9 @@ static int ipq9574_edma_setup_ring_resources(struct ipq9574_edma_hw *ehw)
for (j = 0; j < rxfill_ring->count; j++) {
rxfill_desc = IPQ9574_EDMA_RXFILL_DESC(rxfill_ring, j);
rxfill_desc->rdes0 = virt_to_phys(rx_buf);
rxfill_desc->rdes1 = 0;
rxfill_desc->rdes2 = 0;
rxfill_desc->rdes3 = 0;
rx_buf += PKTSIZE_ALIGN;
pr_debug("Ring %d: rxfill ring dis0 ptr = %p, rxfill ring dis0 dma = %u\n",
j, rxfill_desc, (unsigned int)rxfill_desc->rdes0);
@ -813,6 +816,13 @@ static int ipq9574_edma_setup_ring_resources(struct ipq9574_edma_hw *ehw)
for (j = 0; j < txdesc_ring->count; j++) {
tx_desc = IPQ9574_EDMA_TXDESC_DESC(txdesc_ring, j);
tx_desc->tdes0 = virt_to_phys(tx_buf);
tx_desc->tdes1 = 0;
tx_desc->tdes2 = 0;
tx_desc->tdes3 = 0;
tx_desc->tdes4 = 0;
tx_desc->tdes5 = 0;
tx_desc->tdes6 = 0;
tx_desc->tdes7 = 0;
tx_buf += IPQ9574_EDMA_TX_BUFF_SIZE;
pr_debug("Ring %d: txdesc ring dis0 ptr = %p, txdesc ring dis0 dma = %u\n",
j, tx_desc, (unsigned int)tx_desc->tdes0);
@ -1928,7 +1938,7 @@ int ipq9574_edma_init(void *edma_board_cfg)
mode = fdtdec_get_uint(gd->fdt_blob, node, "switch_mac_mode0", -1);
if (mode < 0) {
printf("Error:switch_mac_mode not specified in dts");
printf("Error:switch_mac_mode0 not specified in dts");
return mode;
}
#endif
@ -2072,6 +2082,7 @@ int ipq9574_edma_init(void *edma_board_cfg)
break;
#endif
default:
printf("\nphy id not matching, calling default qca807x ops");
ipq_qca8075_phy_map_ops(&ipq9574_edma_dev[i]->ops[phy_id]);
break;
}

2
drivers/net/ipq9574/ipq9574_edma.h
View file

@ -19,7 +19,7 @@
#define __IPQ9574_EDMA__
#define IPQ9574_NSS_DP_START_PHY_PORT 1
#define IPQ9574_NSS_DP_MAX_PHY_PORTS 7
#define IPQ9574_NSS_DP_MAX_PHY_PORTS 6
#define IPQ9574_EDMA_BUF_SIZE 2000
#define IPQ9574_EDMA_DEVICE_NODE_NAME "edma"

2
drivers/net/ipq_common/ipq_phy.h
View file

@ -18,7 +18,7 @@
#include <net.h>
#define PHY_MAX 6
#define IPQ9574_PHY_MAX 7
#define IPQ9574_PHY_MAX 6
#define IPQ6018_PHY_MAX 5
#define MDIO_CTRL_0_REG 0x00090040
#define MDIO_CTRL_0_DIV(x) (x << 0)