We used to configure SFP RX pin with 8MA drive strenght and pull
up enabled, but later identified that, it is not really required.
Then, removed it in miami.
But, looks likes when device like SFP-80M module is connected to
SFP cage, these configurations are needed. So, enabling it on
all miami sfp rdps.
This change wont affect our SFP-30M module behaviour.
Change-Id: I5dd758e1d982062d9a0259b50e1e537eeda8ddc8
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
(cherry picked from commit b66a91afdd)
This change force sets the default state for SFP TX pin.
Change-Id: Iaaee73b8c4a6a4abc5fba9b1f88a2225cb1ed39d
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
Since only Q6/TME/TZ should have access to memnoc clock,
so removing the MEMNOC clock enable sequence.
Change-Id: Iee32a59c340cda794b8ee3c314be871ab749ff79
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
skip printing the partition info in smem if it exceeds flash size
Change-Id: Icb13b8d8f0f25f7817dfce2ee42d327081cbbfa6
Signed-off-by: Sridharan S N <quic_sridsn@quicinc.com>
This patch updates the following ethernet configuration
on ipq9574.
Previously, AL06 has qca8075 PHY attached in the UNIPHY0,
now it has been replaced with qca808x PHY mode.
Change-Id: Ieb5b9ef10bd1ebfd1992cbfa10cb02b2ac4d0534
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
RDP467 is same as AL02-C4 with PCIE0 enabled with
wkk support.
Change-Id: If6ba645b7c62a3320139a7c86e0b89ec525a0fb7
Signed-off-by: Saahil Tomar <quic_saahtoma@quicinc.com>
Signed-off-by: Hariharan K <quic_harihk@quicinc.com>
This patch add supports to boot linux 6.1 images on
IPQ5332 & IPQ9574 DB boards.
Change-Id: Ifd9fb1b74c248ffc625c7c49fc96dd7d16a8670f
Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
Update SDX reset GPIO to restart SDX during different SSR scenarios.
Change-Id: I8ecda7f08bbb00498736925efb6bc0f834da48a8
Signed-off-by: Amandeep Singh <quic_amansing@quicinc.com>
This patch appends the rdp474 name of ap-mi01.9 in config
Change-Id: If97ced31402d4f7bb84fb27f7eb4d53e4f4edfd7
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
Reuse DB-MI02.1 for 256M DDR and single QCN64xx radio configuration
Change-Id: Ia08a7705e5254b59cb8f15f5bcba41497fc3eb94
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This RDP is based on AL02-C4, with changes in ethernet for GPON enablement
Change-Id: Ic25d9009e685d8646564bda582305fbf1bce2be6
Signed-off-by: Saahil Tomar <quic_saahtoma@quicinc.com>
Add support to read the TME-l OEM fuse parameters from
qfprom address
Change-Id: Ia4f0766a68b67fccc59a09883dd7ef11bc970eef
Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
The AP-MI01.9 is similar to AP-MI01.2 with internal
radio disabled and pcie0 for WKK 5G and pcie1 for WKK 2G
Change-Id: I568c4da0c7604881395dad08be42201fdf9c746b
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
In AP-MI01.3 RDP, PCIe0 and PCIe1 are enabled in single
lane configuration
Change-Id: I5592d50ebb425a92ad536142573d09cdd60206b2
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch updates the PCIe1 lane configuration for DB-MI01.1
and DB-MI02.1
Change-Id: I3dc15a3255d74fcbd5147b2fa6f89c184e48410b
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch updates the AP-MI04.1 PCIe configuration from
PCIe0 and PCIe1 to PCIe1 and PCIe2
Change-Id: If4aa155cc1005becd050fbc36d91d3764005c4c4
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch adds the ethernet support for AP-MI01.3 and
removes pci nodes from dts
Change-Id: I3fcb338a061d732b44409aa835a1fde45508be95
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch adds the support for AP-MI01.6-QCN9160 RDP by reusing
the ipq5332-mi01.6.dts for better readabilty
Change-Id: I2776222fd80637f0111dc9074491f351cfb932b3
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This patch adds a condition to power cycle the
SDX based on the current status of the e911 call.
Change-Id: Id3cf50cfb49a26151c98b7d52e18b9c487cfb935
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
This patch removes the pcie2 and usb 3.0 support in AP-MI01.2-QCN9160
Change-Id: I1c2a6c9d27f1d2c75d3be505076626396d4c9d37
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
This change set SGMII mode and force mode based on
dts entries.
Change-Id: Ideaa1bb77fe8fb37a7e6b907a987f6dcac54917f
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
This changes enable both PHY and switch configure
simultaneously and also switch can be configure
to any port.
And also these changes enable dual MDIO bus support.
Change-Id: Ib86c8a15abb9a7a35aa86d87cef78ad917dd1a00
Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
AL02-C17 is based on AL02-C4. This variant
enables PCie0 and PCie2.
Change-Id: I67aa500bd13ec661a43b17c4cbcd56c9a6db8abc
Signed-off-by: Saahil Tomar <quic_saahtoma@quicinc.com>
