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Merge "ipq: spi: Enable SPI clocks in Uboot based on QUP id"

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Linux Build Service Account 2023-05-23 22:46:20 -07:00 • committed by Gerrit - the friendly Code Review server
commit 3dd8222d70
8 changed files with 73 additions and 31 deletions
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53
arch/arm/include/asm/arch-qca-common/clk.h
View file

@ -16,6 +16,10 @@
#ifndef CLK_H
#define CLK_H
#define CMD_UPDATE 0x1
#define ROOT_EN 0x2
#define CLK_ENABLE 0x1
/* I2C clocks configuration */
#ifdef CONFIG_IPQ_I2C
@ -61,13 +65,54 @@
(GCC_BLSP1_QUP1_I2C_APPS_CBCR):\
(GCC_BLSP1_QUP2_I2C_APPS_CBCR + (GCC_BLSP1_QUP_I2C_OFFSET_INC * (id-1))))
#define CMD_UPDATE 0x1
#define ROOT_EN 0x2
#define CLK_ENABLE 0x1
void i2c_clock_config(void);
#endif
/* SPI clocks configuration */
#ifdef CONFIG_QCA_SPI
/* IPQ5018, IPQ6018, IPQ807X */
#if defined(CONFIG_IPQ5018) || defined(CONFIG_IPQ6018) || defined(CONFIG_IPQ807x)
#define GCC_BLSP1_QUP1_SPI_APPS_CBCR 0x1802004
#define GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR 0x1802024
#define GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR 0x1802028
#define GCC_BLSP1_QUP2_SPI_APPS_CBCR 0x180300C
#define GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR 0x1803014
#define GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR 0x1803018
#else /* IPQ9574, IPQ5332, devsoc */
#define GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR 0x1802004
#define GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR 0x1802008
#define GCC_BLSP1_QUP1_SPI_APPS_CBCR 0x1802020
#define GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR 0x1803004
#define GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR 0x1803008
#define GCC_BLSP1_QUP2_SPI_APPS_CBCR 0x1803020
#endif
#define GCC_BLSP1_QUP_SPI_OFFSET_INC 0x1000
#define GCC_BLSP_QUP_SPI_SRC_SEL (0x1 << 8) /*Configured for 50MHz*/
#define GCC_BLSP_QUP_SPI_SRC_DIV (0x1F << 0)
#define GCC_BLSP1_QUP_SPI_APPS_CMD_RCGR(id) ((id < 1) ? \
(GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR):\
(GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR + (GCC_BLSP1_QUP_SPI_OFFSET_INC * (id-1))))
#define GCC_BLSP1_QUP_SPI_APPS_CFG_RCGR(id) ((id < 1) ? \
(GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR):\
(GCC_BLSP1_QUP2_SPI_APPS_CFG_RCGR + (GCC_BLSP1_QUP_SPI_OFFSET_INC * (id-1))))
#define GCC_BLSP1_QUP_SPI_APPS_CBCR(id) ((id < 1) ? \
(GCC_BLSP1_QUP1_SPI_APPS_CBCR):\
(GCC_BLSP1_QUP2_SPI_APPS_CBCR + (GCC_BLSP1_QUP_SPI_OFFSET_INC * (id-1))))
void spi_clock_init(int id);
#endif
#endif /*CLK_H*/

19
board/qca/arm/common/clk.c
View file

@ -58,6 +58,25 @@ void i2c_clock_config(void)
}
#endif
#ifdef CONFIG_QCA_SPI
void spi_clock_init(int spi_id)
{
int cfg;
/* Configure qup1_spi_apps_clk_src */
cfg = (GCC_BLSP_QUP_SPI_SRC_SEL |
GCC_BLSP_QUP_SPI_SRC_DIV);
writel(cfg, GCC_BLSP1_QUP_SPI_APPS_CFG_RCGR(spi_id));
writel(CMD_UPDATE, GCC_BLSP1_QUP_SPI_APPS_CMD_RCGR(spi_id));
mdelay(100);
writel(ROOT_EN, GCC_BLSP1_QUP_SPI_APPS_CMD_RCGR(spi_id));
/* Configure CBCR */
writel(CLK_ENABLE, GCC_BLSP1_QUP_SPI_APPS_CBCR(spi_id));
}
#endif
#if defined(CONFIG_QPIC_NAND) && defined(CONFIG_QSPI_SERIAL_TRAINING)
__weak void qpic_set_clk_rate(unsigned int clk_rate, int blk_type,
int req_clk_src_type)

1
board/qca/arm/ipq5018/ipq5018.c
View file

@ -720,6 +720,7 @@ void board_nand_init(void)
gpio_node = fdt_path_offset(gd->fdt_blob, "/spi/spi_gpio");
if (gpio_node >= 0) {
qca_gpio_init(gpio_node);
spi_clock_init(0);
#ifdef CONFIG_MTD_DEVICE
ipq_spi_init(CONFIG_IPQ_SPI_NOR_INFO_IDX);
#endif

1
board/qca/arm/ipq5332/ipq5332.c
View file

@ -914,6 +914,7 @@ void board_nand_init(void)
gpio_node = fdt_path_offset(gd->fdt_blob, "/spi/spi_gpio");
if (gpio_node >= 0) {
qca_gpio_init(gpio_node);
spi_clock_init(0);
#ifdef CONFIG_MTD_DEVICE
ipq_spi_init(CONFIG_IPQ_SPI_NOR_INFO_IDX);
#endif

21
board/qca/arm/ipq6018/ipq6018.c
View file

@ -261,25 +261,6 @@ int board_mmc_init(bd_t *bis)
}
#endif
#ifdef CONFIG_QCA_SPI
static void spi_clock_init(void)
{
int cfg;
/* Configure qup1_spi_apps_clk_src */
cfg = (GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_SEL |
GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV);
writel(cfg, GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR);
writel(CMD_UPDATE, GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR);
mdelay(100);
writel(ROOT_EN, GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR);
/* Configure CBCR */
writel(CLK_ENABLE, GCC_BLSP1_QUP1_SPI_APPS_CBCR);
}
#endif
void board_nand_init(void)
{
#ifdef CONFIG_QCA_SPI
@ -289,10 +270,10 @@ void board_nand_init(void)
qpic_nand_init(NULL);
#ifdef CONFIG_QCA_SPI
spi_clock_init();
gpio_node = fdt_path_offset(gd->fdt_blob, "/spi/spi_gpio");
if (gpio_node >= 0) {
qca_gpio_init(gpio_node);
spi_clock_init(0);
ipq_spi_init(CONFIG_IPQ_SPI_NOR_INFO_IDX);
}
#ifdef CONFIG_SPI_NAND

7
board/qca/arm/ipq6018/ipq6018.h
View file

@ -238,13 +238,6 @@
#define GCC_PCIE0_PHY_PIPE_MISC_SRC_SEL (0x1 << 8)
#define GCC_PCIE0_PHY_PIPE_MISC 0x187501C
#define GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR 0x1802028
#define GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_SEL (1 << 8)
#define GCC_BLSP1_QUP1_SPI_APPS_CFG_RCGR_SRC_DIV (0x1F << 0)
#define GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR 0x1802024
#define GCC_BLSP1_QUP1_SPI_APPS_CBCR 0x1802004
#define set_mdelay_clearbits_le32(addr, value, delay) \
setbits_le32(addr, value); \
mdelay(delay); \

1
board/qca/arm/ipq807x/ipq807x.c
View file

@ -797,6 +797,7 @@ void board_nand_init(void)
gpio_node = fdt_path_offset(gd->fdt_blob, "/spi/spi_gpio");
if (gpio_node >= 0) {
qca_gpio_init(gpio_node);
spi_clock_init(0);
} else {
/* Setting default values */
for (i = 0; i < gboard_param.spi_nor_cfg.gpio_count; i++)

1
board/qca/arm/ipq9574/ipq9574.c
View file

@ -84,6 +84,7 @@ void board_nand_init(void)
gpio_node = fdt_path_offset(gd->fdt_blob, "/spi/spi_gpio");
if (gpio_node >= 0) {
qca_gpio_init(gpio_node);
spi_clock_init(0);
ipq_spi_init(CONFIG_IPQ_SPI_NOR_INFO_IDX);
}
#endif