The RTL931X CMU code was only capable of setting up ring PLL. This is
fine so far as most modes use this PLL type. Other modes are not handled
by the code, neither here nor in the SDK. Though, the SDK has the needed
sequence to setup the LC PLL. Using LC PLL seems to be handled somewhere
else.
Include the small sequence from the SDK to have it, though not used yet.
This could be helpful for further development which goes beyond the SDK.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21707
Signed-off-by: Robert Marko <robimarko@gmail.com>
The implementations for CMU management for RTL930x and RTL931x differ in
their terminology but not that much in their technical aspect. For both
it seems to be the case that two adjacent SerDes share a CMU. This CMU
contains a ring PLL for low speeds (capable of 1G/2.5G) and an LC PLL for
high speeds (capable of 1G/2.5G/10G).
Introduce an enum for the PLL type, used for both RTL93xx variants.
Align the naming of internal variables, especially in the RTL931x
implementation. Rename cmu_type to pll_type because this is much more
accurate. Use 'force_' instead of 'frc_' to make clear what it means.
Also rename the function from 'cmu_type_set' to 'config_cmu' because it
obviously does more than just setting the CMU type but rather configures
the CMU.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21707
Signed-off-by: Robert Marko <robimarko@gmail.com>
Fix the wrong values bit values when setting CMU band which were the
same for both 'enable == true' and 'enable == false'.
While at it, fix some coding issues in the CMU functions:
- drop confusing debug output
- use ternary value instead of if-else
- return proper error
- make variable declaration in reverse christmas tree
- drop unneeded temporary value
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21707
Signed-off-by: Robert Marko <robimarko@gmail.com>
Switch the CMU setup functions to use the SerDes hardware mode instead
of the PHY interface mode.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21707
Signed-off-by: Robert Marko <robimarko@gmail.com>
The symbol error reset function misses the default sequence. E.g. kernel
spits the message "rtpcs_930x_sds_sym_err_reset unsupported phy mode" when
working on 2500base-x.
Align the function with the SDK by
- adding QSGMII mode
- adding the "all other modes" switch
- working with "channels" to make clearer what happens
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21718
Signed-off-by: Robert Marko <robimarko@gmail.com>
The Zyxel GS1900-24 B1 is a 24 port switch with two SFP ports, it is
identical to the A1 except for doubling the ram.
Specifications
--------------
* Device: Zyxel GS1900-24 B1
* SoC: Realtek RTL8382M 500 MHz MIPS 4KEc
* Flash: 16 MiB
* RAM: 128 MiB DDR2 SDRAM
* Ethernet: 24x 10/100/1000 Mbps, 2x SFP 100/1000 Mbps
* LEDs:
* 1 PWR LED (green, not configurable)
* 1 SYS LED (green, configurable)
* 24 ethernet port link/activity LEDs (green, SoC controlled)
* 2 SFP status/activity LEDs (green, SoC controlled)
* Buttons:
* 1 "RESET" button on front panel (soft reset)
* 1 button ('SW1') behind right hex grate (hardwired power-off)
* Power: 120-240V AC C13
* UART: Internal populated 10-pin header ('J5') providing RS232;
connected to SoC UART through a SIPEX 3232EC for voltage
level shifting.
* 'J5' RS232 Pinout (dot as pin 1):
2) SoC RXD
3) GND
10) SoC TXD
Serial connection parameters: 115200 8N1.
Installation
------------
OEM upgrade method:
* Log in to OEM management web interface
* Navigate to Maintenance > Firmware > Management
* If "Active Image" has the first option selected, OpenWrt will need to be
flashed to the "Active" partition. If the second option is selected,
OpenWrt will need to be flashed to the "Backup" partition.
* Navigate to Maintenance > Firmware > Upload
* Upload the openwrt-realtek-rtl838x-zyxel_gs1900-24-b1-initramfs-kernel.bin
file by your preferred method to the previously determined partition.
When prompted, select to boot from the newly flashed image, and reboot
the switch.
* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:
> sysupgrade /tmp/openwrt-realtek-rtl838x-zyxel_gs1900-24-b1-squashfs-sysupgrade.bin
U-Boot TFTP method:
* Configure your client with a static 192.168.1.x IP (e.g. 192.168.1.10).
* Set up a TFTP server on your client and make it serve the initramfs
image.
* Connect serial, power up the switch, interrupt U-boot by hitting the
space bar, and enable the network:
> rtk network on
> Since the GS1900-24 B1 is a dual-partition device, you want to keep the
OEM firmware on the backup partition for the time being. OpenWrt can
only be installed in the first partition anyway (hardcoded in the
DTS). To ensure we are set to boot from the first partition, issue the
following commands:
> setsys bootpartition 0
> savesys
* Download the image onto the device and boot from it:
> tftpboot 0x81f00000 192.168.1.10:openwrt-realtek-rtl838x-zyxel_gs1900-24-b1-initramfs-kernel.bin
> bootm
* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:
> sysupgrade /tmp/openwrt-realtek-rtl838x-zyxel_gs1900-24-b1-squashfs-sysupgrade.bin
Co-authored-by: Goetz Goerisch <ggoerisch@gmail.com>
Signed-off-by: Joe Holden <jwh@zorins.us>
Add memory size and adapt supported device.
Signed-off-by: Goetz Goerisch <ggoerisch@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21595
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
As there are actually 2 versions of the GS1900-24 where the only
difference is the amount of ram, use a common dtsi and make the
original A1 model dts include the dtsi and only override the memory size.
Signed-off-by: Joe Holden <jwh@zorins.us>
Move memory size to device dts.
Signed-off-by: Goetz Goerisch <ggoerisch@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21595
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The ethernet driver uses an indirection for access to the MAC_PORT_CTRL
register (aka. MAC_L2_PORT_CTRL on RTL93xx). It defines the base address
and adds up the cpu port offset. This is not needed as the driver does
not handle the non-cpu ports. Use direct register access instead and
avoid register confusion by always using the "_L2_" naming.
While we are here:
- Drop the functions and use defines instead
- Add CPU port defines for better readability
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21691
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Align with the other Realtek switch drivers and use "ctrl" instead
of "priv" for the central data structure.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21701
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Setup for DSA QOS on RTL839x accesses unitialized memory. For some
reason the handover of the priv structure was realized via global
intermediate variable switch_priv. During refactoring for adbb9a6
("realtek: dsa: rtl83xx: fix init section mismatch") this was not
noticed. Since then RTL839x devices crash during startup.
Fix this by using standard handover via function parameters.
Fixes: adbb9a6 ("realtek: dsa: rtl83xx: fix init section mismatch")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21703
Signed-off-by: Robert Marko <robimarko@gmail.com>
Align the functions with rest of driver.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21685
Signed-off-by: Robert Marko <robimarko@gmail.com>
Align the functions with rest of driver.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21685
Signed-off-by: Robert Marko <robimarko@gmail.com>
There are some code pieces that determine the SoC version of the
running system. For RTL83xx it reads out the registers, for RTL93xx
it simply uses a constant value. Without any consumer of this data
drop it.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21684
Signed-off-by: Robert Marko <robimarko@gmail.com>
No one has looked into the firmware based RTL8218B initializations
for a long time. Instead the basic setup sequences have evolved
so that they can start the RTL8218B PHY from scratch. See
19bc6e8 ("realtek: phy: add basic RTL8218B setup")
4fa90d8 ("realtek: phy: enhance RTL8218B initialization")
Drop the legacy coding.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21679
Signed-off-by: Robert Marko <robimarko@gmail.com>
Compilation currently spits this message:
WARNING: modpost: vmlinux: section mismatch in reference:
rtl83xx_sw_probe+0x6a4 (section: .text.rtl83xx_sw_probe)
-> rtl83xx_setup_qos (section: .init.text)
That means that we have a "normal" function caller (can be
called during the whole uptime) and a "initialization" function
callee (only available during init.
Fix this and directly fix the unwanted family checks.
Fixes: a91c3ab ("realtek: dsa: avoid use-after-free")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21690
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add a PHY ID for Aquantia AQR813 which is an Octa-PHY found in some
Realtek switches.
Add another PHY ID for another revision of AQR113C, also found in some
Realtek switches.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21515
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Apply the PHY polling configuration for RTL931x too, as previously
implemented for RTL930x. This is needed for several PHYs on that
platform to function properly.
Add another flag called 'force_res' to the phy_info struct which is for
RTL931x only. The SDK mentions this as a flag to force polling the
Realtek proprietary PHY status resolution register. Effectively, this
changes the polling to proprietary format instead of standard format,
and sets an enable bit in another private polling register field.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21515
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reading the PHY ID to assign a PHY config is currently simple. For C45
two MDIO reads of a hardcoded MMD are done to get the standard PHY ID
registers. MMD 31 (MMD_VEND2) is used for that purpose, assuming there
will be a valid PHY ID stored in this MMD in all cases. However, with
Aquantia AQR813 there's at least one example for which this isn't true.
This PHY returns 0 for the PHY ID in MMD_VEND2, instead MMD_VEND1 would
have the correct ID.
Enhance reading the PHY by accessing a common set of MMDs of which most
PHY at least implement one and have a valid PHY ID in. To keep overhead
low, do not scan all MMDs. As soon as a valid PHY ID is found, exit and
use that. This is similar to the kernel logic, jsut reduced to fewer
MMDs.
Also handle possible errors coming from MDIO reads to avoid reading garbage.
While at it, move reading the PHY ID to a separate function to not
pollute the poll fixup retrievel function.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21515
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
The Realtek mdio driver does not need to track a separate lock.
Rely on the default kernel mdio bus lock instead.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21529
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Refactor RTL931x mdio commands to use the new helper function.
Remove unneeded goto and debug statements.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21529
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Refactor RTL930x mdio commands to use the new helper function.
Remove unneeded goto and debug statements.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21529
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Refactor RTL839x mdio commands to use the new helper function.
Remove unneeded goto and debug statements.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21529
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The Realtek mdio bus works similar for all devices with only
minor family specific differences. Basically command issuing
follows a generic style. Write command type and a trigger.
Afterwards wait until the trigger flag goes back to zero (aka
"command complete"). Unify this sequence in a central helper.
RTL838x read/write callers of this helper use a strange style of
error handling by issuing goto statements. Refactor this for better
readability. Additionally remove all debug prints. These are not
needed as the central read/write handlers provide a common logging
mechanism.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21529
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
A phy is configured in two stages
- phy_probe() for setup of structures
- config_init() for device setup (after reset)
RTL8214FC is a combo phy and the currently active port can be switched
with the SFP helper functions that are triggered during SFP insertion
and removal. In case a fibre SFP is inserted while booting the SFP
trigger is run between the above mentioned stages. During the final
setup in config_init() the phy is reset to the copper port. Thus no
link is available on fibre and the SFP must be reinserted for normal
operation.
For a consistent behaviour the fibre/copper port setup must run before
the SFP probing and not afterwards. Move the setup code from config_init()
into phy_probe().
Fixes: 10ae743 ("realtek: phy: simplify RTL8214FC configuration")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21582
Signed-off-by: Robert Marko <robimarko@gmail.com>
There are some shortcomings in rtl8214fc_media_set()
- It always uses the mdio raw page (4095) of RTL838x for writes.
That is wrong when the phy is attached to an RTL839x (raw = 8191)
- It uses the internal write only extended page companion (29)
- The extended page content is not preserved
Fix the three issues.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Changing the fibre/copper power of a RTL8214FC changes the
extended page via register 29. This is the write only companion
of register 30. The register is afterwards overwritten to 0.
Use the proper extended page register 30 and preserve its content
during the operation.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Bit 11 of registers 16, 19, 20, 21 in page 0x266 denotes if a port
of a RTL8214FC is set/favoured to fibre (0) or copper (1). For unknown
reasons the bit was mixed with BMCR_PDOWN. Convert this to a meaningful
define.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21582
Signed-off-by: Robert Marko <robimarko@gmail.com>
There is a misunderstanding about BIT(7) aka EX_PHY_MAN_24_27 in
SMI_GLB_CTRL register. The SDK sets/clears it at different places and
it is not clear what it is for. Observation shows that it is essential
for a working MAC_LINK_MEDIA_STS register.
A RTL838x device has usally two configurations
- port 24/26 are 2 serdes driven fiber ports
- port 24-27 are 4 PHY driven combo ports
In the combo case the above bit must be set so that a switch between
copper and fiber can be detected. Cleanup the MDIO initialization
and remove the unneeded bit handling in the DSA driver.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21653
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL8218D currently relies on proper U-Boot configuration. In
case that is not possible, provide a basic setup sequence that can
bring the PHY "alive". The SDK provides multiple configuration
sequences for two operation modes (XSGMII or QSGMII) and the different
SoC families. Due to limited testing resources only provide a setup
for RTL93xx devices and both modes at the moment.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21551
Signed-off-by: Robert Marko <robimarko@gmail.com>
The dts for RTL93xx devices has duplicate data about the
smi bus of a phy node. The parent node declares the number
of the bus and the realtek,smi-address attribute does the
same.
Remove the bus part from the realtek,smi-address attribute
and lookup the bus from the parent node. While we are here
remove all realtek,smi-address attributes where phy id
matches the bus address. The driver will use that as a
fallback.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21438
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Switch the mdio bus topology for devices that have their phys
attached to bus 1-3. This does not have any impact because
the mdio driver was completly redisgned
With this commit the bus id is stored twice. Once in the (new)
bus and in the (old) realtek,smi-address property. E.g.
&mdio_bus1 {
reg = <1>; <<< bus id
phy24: ethernet-phy@24 {
reg = <26>;
compatible = "ethernet-phy-ieee802.3-c22";
realtek,smi-address = <1 2>; <<< bus & address id
};
};
This redundancy will be removed later.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21438
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
RTL93xx devices have 4 smi busses (0-3). Add them to the dts.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21438
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The mdio driver currently determines the smi bus and address from the
realtek,smi-address attribute of the phy. To better reflect the
topology and align with upstream, the phys should be relocated below
their associated bus. As an interim solution the following dts notation
is in focus.
mdio_ctrl: mdio-controller {
mdio_bus0: mdio-bus@0 {
reg = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <8>;
};
&mdio_bus1 {
reg = <1>;
phy16: ethernet-phy@16 {
reg = <16>;
compatible = "ethernet-phy-ieee802.3-c45";
realtek,smi-address = <2>;
};
}
With this
- the phy reg property still denotes the port number
- the bus number can be derived from the parent bus node.
- the bus address is taken from realtek,smi-address
Refactor bus initialization so it can handle phy nodes below
multiple bus nodes.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21438
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
During initialization the mdio driver registers phys with the
iterator "pn". To make clear that it is a phy address rename it
to "addr".
While we are here improve the upper bound check of the maximum
possible address. This is the family specific cpu port and not
the generic upper bound constant for all devices.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21438
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
In the future the mdio controller will have multiple busses
defined in the dts below the controller node. Nevertheless
it will still hand out only one single bus to the kernel.
Attach the (exported) bus to the controller node instead of
the single (dts) bus subnode.
With this change the mdio lookup in the dsa driver must
be changed to point to the mdio controller node too.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21438
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The device specific stp_get() functions can return the state
of a given port individually. No need to disassemble the
device specific state table. Additionally change function
prefix.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21527
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The family specific stp_get() functions have a new return value
that gives the stp status of a given port. Instead of a constant
zero value provide the real data.
While we are here align the RTL930x implementation with the
other ones.
- Drop the debug output
- Make use of priv->r->tbl_access_data_0()
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21527
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The device specific stp_get() function returns a device specific
state to the generic caller. So the caller must use a if/else
statement depending on the family to look into the retrieved data.
Change the signature of the function so it can return a device
independent state of a given port in the future. Additionally
use the new function prefix.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21527
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SGMII only works correctly on this device if inband auto-negotiation is
enabled. Configure the PHY for SGMII and in-band mode in the device tree
to make this happen.
For 2.5G link speeds the PHY will still switch to 2500Base-X without AN.
The same configuration also works on RTL8226, so it is fine to apply
this change to the A1 revision of XGS1010-12/XGS1210-12 as well.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/21605
Signed-off-by: Robert Marko <robimarko@gmail.com>
Backport a bunch of upstream commits simplifying the RealTek PHY driver
and re-unifying the C22 and C45 driver instances.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Rework the SerDes mode setting to have a better logical structure,
similar to how RTL931x currently does it. Mode setting is grouped into a
MAC setup and IP core setup. Most modes just need to trigger the MAC
setup and then they work, otherwise some complex sequence is needed.
To achieve that, rename several functions and group their content
differently. While at it, rename some constants to use the RTPCS_ prefix.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21565
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL930x has some helpers which take care of writing the actual mode
value to the corresponding register. They exist for the MAC setup SerDes
mode, the USXGMII submode and the SerDes IP core mode.
To reflect that, adjust the naming of these helpers accordingly. Most
importantly, prefix the helper names with '__'. This is a common
convention to denote helpers/functions which are internal, not intended
for general use and skip certain checks. Those conditions apply to these
helpers. Though they are still used quite often here, this might change
with further cleanups.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21565
Signed-off-by: Robert Marko <robimarko@gmail.com>
Completely replace usage of PHY_INTERFACE_MODE_* in the vast amount of
calibration functions with the SerDes hardware mode.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21565
Signed-off-by: Robert Marko <robimarko@gmail.com>
Set and configure the SerDes mode using the SerDes hardware mode types
instead of PHY_INTERFACE_MODE_*.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21565
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use SerDes hardware mode in RTL930x SerDes TX config instead of
PHY_INTERFACE_MODE_* modes.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21565
Signed-off-by: Robert Marko <robimarko@gmail.com>
Switch to using the SerDes hardware mode in RTL930x SerDes patching aka
rtpcs_930x_sds_patch.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21565
Signed-off-by: Robert Marko <robimarko@gmail.com>
Start using the SerDes hardware in the RTL930x SerDes setup entrypoint.
Use the generic mapper (which will be moved out later to pcs_config) to
determine the mode. In the next steps, switch to solely using that
step-by-step.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21565
Signed-off-by: Robert Marko <robimarko@gmail.com>
Convert the update_counter() and net_irq() functions to the
new prefix. For better readability rename "cntr" to "counter".
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21569
Signed-off-by: Robert Marko <robimarko@gmail.com>
