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realtek: phy: enhance RTL8218B initialization

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The RTL8214FC and the RTL8218B share the same register set and
need to be initialized quite similar. In the future the RTl8214FC
will get its own setup sequence. To keep the codebase small the
common parts (serdes & copper) will be covered by the existing
RTL8218B configuration.

Enhance the RTL8218B setup with this separate commit to ensure
that nothing breaks.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21435
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
This commit is contained in:
Markus Stockhausen 2026-01-07 08:02:40 +01:00 • committed by Stijn Tintel
parent b209174c43
commit 4fa90d879b
1 changed files with 10 additions and 0 deletions
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10
target/linux/realtek/files-6.12/drivers/net/phy/rtl83xx-phy.c
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@ -904,9 +904,19 @@ static int rtl8218b_config_init(struct phy_device *phydev)
phy_modify_paged(phydev, RTL821X_MAC_SDS_PAGE(0, 1), 0x14, 0, BIT(3));
/* magic CMU setting for stable connectivity of first MAC serdes */
phy_write_paged(phydev, 0x462, 0x15, 0x6e58);
/* magic setting for rate select 10G full */
phy_write_paged(phydev, 0x464, 0x15, 0x202a);
/* magic setting for variable gain amplifier */
phy_modify_paged(phydev, 0x464, 0x12, 0, 0x1f80);
/* magic setting for equalizer of second MAC serdes */
phy_write_paged(phydev, RTL821X_MAC_SDS_PAGE(1, 8), 0x12, 0x2020);
/* unknown magic for second MAC serdes */
phy_write_paged(phydev, RTL821X_MAC_SDS_PAGE(1, 9), 0x11, 0xc014);
rtl8218b_cmu_reset(phydev, 0);
for (int sds = 0; sds < 2; sds++) {
/* disable ring PLL for serdes 2+3 */
phy_modify_paged(phydev, RTL821X_MAC_SDS_PAGE(sds + 1, 8), 0x11, BIT(15), 0);
/* force negative clock edge */
phy_modify_paged(phydev, RTL821X_MAC_SDS_PAGE(sds, 0), 0x17, 0, BIT(14));
rtl8218b_cmu_reset(phydev, 5 + sds);