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realtek: use common dtsi for Zyxel GS1900-24
As there are actually 2 versions of the GS1900-24 where the only difference is the amount of ram, use a common dtsi and make the original A1 model dts include the dtsi and only override the memory size. Signed-off-by: Joe Holden <jwh@zorins.us> Move memory size to device dts. Signed-off-by: Goetz Goerisch <ggoerisch@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21595 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Joe Holden
Hauke Mehrtens
parent
1e678eb223
commit
c4cf9da881
2 changed files with 123 additions and 117 deletions
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@ -1,7 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "rtl8380_zyxel_gs1900.dtsi"
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#include "rtl8380_zyxel_gs1900_gpio.dtsi"
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#include "rtl8382_zyxel_gs1900-24.dtsi"
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/ {
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compatible = "zyxel,gs1900-24-a1", "realtek,rtl838x-soc";
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@ -10,119 +9,4 @@
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memory@0 {
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reg = <0x0 0x4000000>;
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};
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/* i2c of the left SFP cage: port 25 */
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i2c0: i2c-gpio-0 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp0: sfp-p25 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
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};
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/* i2c of the right SFP cage: port 26 */
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i2c1: i2c-gpio-1 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp1: sfp-p26 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
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};
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};
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&uart1 {
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status = "okay";
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};
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&mdio_bus0 {
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EXTERNAL_PHY(0)
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EXTERNAL_PHY(1)
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EXTERNAL_PHY(2)
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EXTERNAL_PHY(3)
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EXTERNAL_PHY(4)
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EXTERNAL_PHY(5)
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EXTERNAL_PHY(6)
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EXTERNAL_PHY(7)
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EXTERNAL_PHY(16)
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EXTERNAL_PHY(17)
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EXTERNAL_PHY(18)
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EXTERNAL_PHY(19)
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EXTERNAL_PHY(20)
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EXTERNAL_PHY(21)
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EXTERNAL_PHY(22)
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EXTERNAL_PHY(23)
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};
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&switch0 {
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ports {
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SWITCH_PORT_SDS(0, 1, 0, qsgmii)
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SWITCH_PORT_SDS(1, 2, 0, qsgmii)
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SWITCH_PORT_SDS(2, 3, 0, qsgmii)
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SWITCH_PORT_SDS(3, 4, 0, qsgmii)
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SWITCH_PORT_SDS(4, 5, 1, qsgmii)
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SWITCH_PORT_SDS(5, 6, 1, qsgmii)
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SWITCH_PORT_SDS(6, 7, 1, qsgmii)
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SWITCH_PORT_SDS(7, 8, 1, qsgmii)
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SWITCH_PORT(8, 9, internal)
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SWITCH_PORT(9, 10, internal)
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SWITCH_PORT(10, 11, internal)
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SWITCH_PORT(11, 12, internal)
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SWITCH_PORT(12, 13, internal)
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SWITCH_PORT(13, 14, internal)
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SWITCH_PORT(14, 15, internal)
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SWITCH_PORT(15, 16, internal)
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SWITCH_PORT_SDS(16, 17, 2, qsgmii)
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SWITCH_PORT_SDS(17, 18, 2, qsgmii)
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SWITCH_PORT_SDS(18, 19, 2, qsgmii)
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SWITCH_PORT_SDS(19, 20, 2, qsgmii)
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SWITCH_PORT_SDS(20, 21, 3, qsgmii)
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SWITCH_PORT_SDS(21, 22, 3, qsgmii)
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SWITCH_PORT_SDS(22, 23, 3, qsgmii)
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SWITCH_PORT_SDS(23, 24, 3, qsgmii)
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port@24 {
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reg = <24>;
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label = "lan25";
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pcs-handle = <&serdes4>;
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp0>;
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};
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port@26 {
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reg = <26>;
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label = "lan26";
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pcs-handle = <&serdes5>;
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp1>;
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};
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};
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};
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&gpio1 {
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/delete-node/ poe_enable;
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};
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122
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24.dtsi
Normal file
122
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24.dtsi
Normal file
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@ -0,0 +1,122 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "rtl8380_zyxel_gs1900.dtsi"
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#include "rtl8380_zyxel_gs1900_gpio.dtsi"
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/ {
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/* i2c of the left SFP cage: port 25 */
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i2c0: i2c-gpio-0 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp0: sfp-p25 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
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};
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/* i2c of the right SFP cage: port 26 */
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i2c1: i2c-gpio-1 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp1: sfp-p26 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
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};
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};
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&uart1 {
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status = "okay";
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};
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&mdio_bus0 {
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EXTERNAL_PHY(0)
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EXTERNAL_PHY(1)
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EXTERNAL_PHY(2)
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EXTERNAL_PHY(3)
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EXTERNAL_PHY(4)
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EXTERNAL_PHY(5)
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EXTERNAL_PHY(6)
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EXTERNAL_PHY(7)
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EXTERNAL_PHY(16)
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EXTERNAL_PHY(17)
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EXTERNAL_PHY(18)
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EXTERNAL_PHY(19)
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EXTERNAL_PHY(20)
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EXTERNAL_PHY(21)
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EXTERNAL_PHY(22)
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EXTERNAL_PHY(23)
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};
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&switch0 {
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ports {
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SWITCH_PORT_SDS(0, 1, 0, qsgmii)
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SWITCH_PORT_SDS(1, 2, 0, qsgmii)
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SWITCH_PORT_SDS(2, 3, 0, qsgmii)
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SWITCH_PORT_SDS(3, 4, 0, qsgmii)
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SWITCH_PORT_SDS(4, 5, 1, qsgmii)
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SWITCH_PORT_SDS(5, 6, 1, qsgmii)
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SWITCH_PORT_SDS(6, 7, 1, qsgmii)
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SWITCH_PORT_SDS(7, 8, 1, qsgmii)
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SWITCH_PORT(8, 9, internal)
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SWITCH_PORT(9, 10, internal)
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SWITCH_PORT(10, 11, internal)
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SWITCH_PORT(11, 12, internal)
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SWITCH_PORT(12, 13, internal)
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SWITCH_PORT(13, 14, internal)
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SWITCH_PORT(14, 15, internal)
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SWITCH_PORT(15, 16, internal)
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SWITCH_PORT_SDS(16, 17, 2, qsgmii)
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SWITCH_PORT_SDS(17, 18, 2, qsgmii)
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SWITCH_PORT_SDS(18, 19, 2, qsgmii)
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SWITCH_PORT_SDS(19, 20, 2, qsgmii)
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SWITCH_PORT_SDS(20, 21, 3, qsgmii)
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SWITCH_PORT_SDS(21, 22, 3, qsgmii)
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SWITCH_PORT_SDS(22, 23, 3, qsgmii)
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SWITCH_PORT_SDS(23, 24, 3, qsgmii)
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port@24 {
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reg = <24>;
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label = "lan25";
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pcs-handle = <&serdes4>;
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp0>;
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};
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port@26 {
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reg = <26>;
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label = "lan26";
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pcs-handle = <&serdes5>;
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp1>;
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};
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};
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};
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&gpio1 {
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/delete-node/ poe_enable;
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};
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