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realtek: pcs: rtl93xx: improve CMU terminology
The implementations for CMU management for RTL930x and RTL931x differ in their terminology but not that much in their technical aspect. For both it seems to be the case that two adjacent SerDes share a CMU. This CMU contains a ring PLL for low speeds (capable of 1G/2.5G) and an LC PLL for high speeds (capable of 1G/2.5G/10G). Introduce an enum for the PLL type, used for both RTL93xx variants. Align the naming of internal variables, especially in the RTL931x implementation. Rename cmu_type to pll_type because this is much more accurate. Use 'force_' instead of 'frc_' to make clear what it means. Also rename the function from 'cmu_type_set' to 'config_cmu' because it obviously does more than just setting the CMU type but rather configures the CMU. Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21707 Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Jonas Jelonek
Robert Marko
parent
48ada316f2
commit
638ccb6760
1 changed files with 68 additions and 55 deletions
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@ -101,8 +101,8 @@
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#define RTSDS_930X_PLL_1000 0x1
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#define RTSDS_930X_PLL_10000 0x5
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#define RTSDS_930X_PLL_2500 0x3
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#define RTSDS_930X_PLL_LC 0x3
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#define RTSDS_930X_PLL_RING 0x1
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#define RTPCS_930X_PLL_LC 0x3
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#define RTPCS_930X_PLL_RING 0x1
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/* Registers of the internal SerDes of the 9310 */
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#define RTL931X_SERDES_MODE_CTRL (0x13cc)
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@ -146,6 +146,12 @@ enum rtpcs_port_media {
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RTPCS_PORT_MEDIA_DAC_500CM,
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};
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enum rtpcs_sds_pll_type {
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RTPCS_SDS_PLL_RING,
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RTPCS_SDS_PLL_LC,
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RTPCS_SDS_PLL_END,
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};
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struct rtpcs_ctrl;
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struct rtpcs_serdes {
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@ -977,38 +983,42 @@ static void rtpcs_930x_sds_rx_reset(struct rtpcs_serdes *sds,
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rtpcs_sds_write_bits(sds, page, 0x15, 4, 4, 0x0);
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}
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static void rtpcs_930x_sds_get_pll_data(struct rtpcs_serdes *sds,
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int *pll, int *speed)
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static void rtpcs_930x_sds_get_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type *pll,
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int *speed)
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{
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struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds);
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int sbit, pbit = (sds == even_sds) ? 4 : 6;
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int pll_val;
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/*
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* PLL data is shared between adjacent SerDes in the even lane. Each SerDes defines
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* what PLL it needs (ring or LC) while the PLL itself stores the current speed.
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*/
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*pll = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, pbit + 1, pbit);
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sbit = *pll == RTSDS_930X_PLL_LC ? 8 : 12;
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pll_val = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, pbit + 1, pbit);
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*pll = pll_val == RTPCS_930X_PLL_LC ? RTPCS_SDS_PLL_LC : RTPCS_SDS_PLL_RING;
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sbit = *pll == RTPCS_SDS_PLL_LC ? 8 : 12;
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*speed = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, sbit + 3, sbit);
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}
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static int rtpcs_930x_sds_set_pll_data(struct rtpcs_serdes *sds,
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int pll, int speed)
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static int rtpcs_930x_sds_set_pll_data(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll,
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int speed)
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{
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struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds);
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int sbit = pll == RTSDS_930X_PLL_LC ? 8 : 12;
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int sbit = pll == RTPCS_SDS_PLL_LC ? 8 : 12;
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int pbit = (sds == even_sds) ? 4 : 6;
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int pll_val;
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if ((speed != RTSDS_930X_PLL_1000) &&
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(speed != RTSDS_930X_PLL_2500) &&
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(speed != RTSDS_930X_PLL_10000))
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return -EINVAL;
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if ((pll != RTSDS_930X_PLL_RING) && (pll != RTSDS_930X_PLL_LC))
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if (pll >= RTPCS_SDS_PLL_END)
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return -EINVAL;
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if ((pll == RTSDS_930X_PLL_RING) && (speed == RTSDS_930X_PLL_10000))
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if ((pll == RTPCS_SDS_PLL_RING) && (speed == RTSDS_930X_PLL_10000))
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return -EINVAL;
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/*
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@ -1017,8 +1027,9 @@ static int rtpcs_930x_sds_set_pll_data(struct rtpcs_serdes *sds,
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* always activate both.
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*/
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pll_val = pll == RTPCS_SDS_PLL_LC ? RTPCS_930X_PLL_LC : RTPCS_930X_PLL_RING;
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rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 3, 0, 0xf);
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rtpcs_sds_write_bits(even_sds, 0x20, 0x12, pbit + 1, pbit, pll);
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rtpcs_sds_write_bits(even_sds, 0x20, 0x12, pbit + 1, pbit, pll_val);
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rtpcs_sds_write_bits(even_sds, 0x20, 0x12, sbit + 3, sbit, speed);
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return 0;
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@ -1028,7 +1039,8 @@ static void rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds)
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{
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struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds);
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int reset_sequence[4] = { 3, 2, 3, 1 };
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int pll, speed, i, bit;
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enum rtpcs_sds_pll_type pll;
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int speed, i, bit;
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/*
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* After the PLL speed has changed, the CMU must take over the new values. The models
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@ -1037,7 +1049,7 @@ static void rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds)
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*/
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rtpcs_930x_sds_get_pll_data(sds, &pll, &speed);
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bit = pll == RTSDS_930X_PLL_LC ? 2 : 0;
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bit = pll == RTPCS_SDS_PLL_LC ? 2 : 0;
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for (i = 0; i < ARRAY_SIZE(reset_sequence); i++)
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rtpcs_sds_write_bits(even_sds, 0x21, 0x0b, bit + 1, bit,
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@ -1089,9 +1101,10 @@ static void rtpcs_930x_sds_set_power(struct rtpcs_serdes *sds, bool on)
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rtpcs_sds_write_bits(sds, 0x20, 0x00, 5, 4, rx_enable);
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}
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static void rtpcs_930x_sds_reconfigure_pll(struct rtpcs_serdes *sds, int pll)
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static void rtpcs_930x_sds_reconfigure_pll(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll)
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{
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int mode, tmp, speed;
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enum rtpcs_sds_pll_type tmp;
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int mode, speed;
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mode = __rtpcs_930x_sds_get_ip_mode(sds);
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rtpcs_930x_sds_get_pll_data(sds, &tmp, &speed);
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@ -1113,9 +1126,9 @@ static int rtpcs_930x_sds_config_pll(struct rtpcs_serdes *sds,
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enum rtpcs_sds_mode hw_mode)
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{
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struct rtpcs_serdes *nb_sds = rtpcs_sds_get_neighbor(sds);
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int neighbor_speed, neighbor_mode, neighbor_pll;
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enum rtpcs_sds_pll_type pll, neighbor_pll;
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int speed, neighbor_speed, neighbor_mode;
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bool speed_changed = true;
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int pll, speed;
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/*
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* A SerDes pair on the RTL930x is driven by two PLLs. A low speed ring PLL can generate
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@ -1150,19 +1163,19 @@ static int rtpcs_930x_sds_config_pll(struct rtpcs_serdes *sds,
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return -ENOTSUPP;
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if (!neighbor_mode)
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pll = speed == RTSDS_930X_PLL_10000 ? RTSDS_930X_PLL_LC : RTSDS_930X_PLL_RING;
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pll = speed == RTSDS_930X_PLL_10000 ? RTPCS_SDS_PLL_LC : RTPCS_SDS_PLL_RING;
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else if (speed == neighbor_speed) {
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speed_changed = false;
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pll = neighbor_pll;
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} else if (neighbor_pll == RTSDS_930X_PLL_RING)
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pll = RTSDS_930X_PLL_LC;
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} else if (neighbor_pll == RTPCS_SDS_PLL_RING)
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pll = RTPCS_SDS_PLL_LC;
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else if (speed == RTSDS_930X_PLL_10000) {
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pr_info("%s: SDS %d needs LC PLL, reconfigure SDS %d to use ring PLL\n",
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__func__, sds->id, nb_sds->id);
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rtpcs_930x_sds_reconfigure_pll(nb_sds, RTSDS_930X_PLL_RING);
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pll = RTSDS_930X_PLL_LC;
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rtpcs_930x_sds_reconfigure_pll(nb_sds, RTPCS_SDS_PLL_RING);
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pll = RTPCS_SDS_PLL_LC;
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} else
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pll = RTSDS_930X_PLL_RING;
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pll = RTPCS_SDS_PLL_RING;
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rtpcs_930x_sds_set_pll_data(sds, pll, speed);
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@ -1170,7 +1183,7 @@ static int rtpcs_930x_sds_config_pll(struct rtpcs_serdes *sds,
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rtpcs_930x_sds_reset_cmu(sds);
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pr_info("%s: SDS %d using %s PLL for mode %d\n", __func__, sds->id,
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pll == RTSDS_930X_PLL_LC ? "LC" : "ring", hw_mode);
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pll == RTPCS_SDS_PLL_LC ? "LC" : "ring", hw_mode);
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return 0;
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}
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@ -2916,14 +2929,14 @@ static int rtpcs_931x_sds_cmu_page_get(enum rtpcs_sds_mode hw_mode)
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}
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}
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static int rtpcs_931x_sds_cmu_type_set(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode,
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int chiptype)
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static int rtpcs_931x_sds_config_cmu(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode,
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int chiptype)
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{
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struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds);
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u32 frc_lc_mode_bitnum, frc_lc_mode_val_bitnum;
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int cmu_type = 0; /* Clock Management Unit */
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u32 force_lc_mode_bit, force_lc_mode_val_bit;
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enum rtpcs_sds_pll_type pll_type; /* SDK calls this cmu_type */
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bool force_pll_spd;
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int cmu_page = 0;
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u32 frc_cmu_spd;
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switch (hw_mode) {
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case RTPCS_SDS_MODE_OFF:
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@ -2943,28 +2956,28 @@ static int rtpcs_931x_sds_cmu_type_set(struct rtpcs_serdes *sds, enum rtpcs_sds_
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return; */
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case RTPCS_SDS_MODE_QSGMII:
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cmu_type = 1;
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frc_cmu_spd = 0;
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pll_type = RTPCS_SDS_PLL_RING;
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force_pll_spd = false;
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break;
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case RTPCS_SDS_MODE_1000BASEX:
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cmu_type = 1;
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frc_cmu_spd = 0;
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pll_type = RTPCS_SDS_PLL_RING;
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force_pll_spd = false;
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break;
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/* case MII_1000BX100BX_AUTO:
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cmu_type = 1;
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frc_cmu_spd = 0;
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pll_type = RTPCS_SDS_PLL_RING;
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force_pll_spd = false;
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break; */
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case RTPCS_SDS_MODE_SGMII:
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cmu_type = 1;
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frc_cmu_spd = 0;
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pll_type = RTPCS_SDS_PLL_RING;
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force_pll_spd = false;
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break;
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case RTPCS_SDS_MODE_2500BASEX:
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cmu_type = 1;
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frc_cmu_spd = 1;
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pll_type = RTPCS_SDS_PLL_RING;
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force_pll_spd = true;
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break;
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default:
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@ -2972,36 +2985,36 @@ static int rtpcs_931x_sds_cmu_type_set(struct rtpcs_serdes *sds, enum rtpcs_sds_
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return -EINVAL;
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}
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if (cmu_type == 1) {
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if (pll_type == RTPCS_SDS_PLL_RING) {
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cmu_page = rtpcs_931x_sds_cmu_page_get(hw_mode);
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if (cmu_page < 0)
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return -EINVAL;
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}
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if (sds == even_sds) {
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frc_lc_mode_bitnum = 4;
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frc_lc_mode_val_bitnum = 5;
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force_lc_mode_bit = 4;
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force_lc_mode_val_bit = 5;
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} else {
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frc_lc_mode_bitnum = 6;
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frc_lc_mode_val_bitnum = 7;
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force_lc_mode_bit = 6;
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force_lc_mode_val_bit = 7;
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}
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pr_info("%s: cmu_type %0d cmu_page %x frc_cmu_spd %d even_sds %d sds %d\n",
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__func__, cmu_type, cmu_page, frc_cmu_spd, even_sds->id,
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sds->id);
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pr_info("%s: pll_type %s cmu_page %x force_pll_spd %d even_sds %d sds %d\n",
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__func__, pll_type == RTPCS_SDS_PLL_LC ? "LC" : "ring", cmu_page, force_pll_spd,
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even_sds->id, sds->id);
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if (cmu_type == 1) {
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if (pll_type == RTPCS_SDS_PLL_RING) {
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rtpcs_sds_write_bits(sds, cmu_page, 0x7, 15, 15, 0x0);
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if (chiptype)
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rtpcs_sds_write_bits(sds, cmu_page, 0xd, 14, 14, 0x0);
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rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 3, 2, 0x3);
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rtpcs_sds_write_bits(even_sds, 0x20, 0x12, frc_lc_mode_bitnum,
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frc_lc_mode_bitnum, 0x1);
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rtpcs_sds_write_bits(even_sds, 0x20, 0x12, frc_lc_mode_val_bitnum,
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frc_lc_mode_val_bitnum, 0x0);
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rtpcs_sds_write_bits(even_sds, 0x20, 0x12, force_lc_mode_bit,
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force_lc_mode_bit, 0x1);
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rtpcs_sds_write_bits(even_sds, 0x20, 0x12, force_lc_mode_val_bit,
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force_lc_mode_val_bit, 0x0);
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rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 12, 12, 0x1);
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rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 15, 13, frc_cmu_spd);
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rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 15, 13, force_pll_spd ? 0x1 : 0x0);
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}
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return 0;
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@ -3431,7 +3444,7 @@ static int rtpcs_931x_setup_serdes(struct rtpcs_serdes *sds,
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break;
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}
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rtpcs_931x_sds_cmu_type_set(sds, hw_mode, chiptype);
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rtpcs_931x_sds_config_cmu(sds, hw_mode, chiptype);
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if (sds_id >= 2) {
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if (chiptype)
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