EDUP EP-RT2960S has the similar hardware design as the SIMAX1800T.
The main difference is the arrangement of the GPIO pins
and the location of the MAC address.
Specification
-------------
- SoC : Mediatek MT7621
- RAM : 256 MiB DDR3
- Flash : 128 MiB NAND Flash
- WLAN : Mediatek MT7905 DBDC
- 2.4 GHz : 2x2 MIMO WiFi6
- 5 GHz : 2x2 MIMO WiFi6
- Ethernet : MT7621 built-in 10/100/1000 Mbps 1x WAN; 3x LAN
- UART : 3.3V, 115200n8
- Buttons : 1x RESET; 1x WPS/MESH
- LEDs : 1x Multi-Color(Blue;Green;Red)
- Power : DC 12V1A
- CMIIT ID : 2022AP7163
- TFTP IP :
- server : 192.168.1.254
- router : 192.168.1.28
TFTP Installation(recommend)
------------
1. Set local tftp server IP "192.168.1.254" and NetMask "255.255.255.0".
2. Rename initramfs-kernel.bin to "factory.bin" and put it in the root
directory of the tftp server. tftpd64 is a good choice for Windows.
3. Remove all Ethernet cables and WiFi connections from the PC, except
for the one connected to the EDUP EP-RT2960S. Start the TFTP server, plug
in the power adapter and wait for the OpenWrt system to boot.
4. Backup "firmware" partition and rename it to "firmware.bin". We need
it to back to the stock firmware.
5. Use "fw_printenv" command to list envs. If "firmware_select=2" is
observed then set u-boot env variable via command:
`fw_setenv firmware_select 1`
6. Apply sysupgrade.bin in OpenWrt LuCI.
Web UI Installation
------------
1. Apply update by uploading initramfs-factory.bin to the web UI.
2. Use "fw_printenv" command to list envs. If "firmware_select=2" is
observed then set u-boot env variable via command:
`fw_setenv firmware_select 1`
3. Apply squashfs-sysupgrade.bin in OpenWrt LuCI.
Return to Stock Firmware
----------------------------
Restore the backup firmware partition in the installation step 4.
MAC addresses
-------------
+---------+-------------------+
| | MAC example |
+---------+-------------------+
| LABEL | 24:D5:1C:xx:xx:xx |
| LAN | 24:D5:1C:xx:xx:xx |
| WAN | 24:D5:1C:xx:xx:xx |
| WLAN2G | 24:D5:1C:xx:xx:xx |
| WLAN5G | 26:D5:1C:xx:xx:xx |
+---------+-------------------+
Tips:
-----------
User can use `TFTP Installation` method to recover a brick device.
Signed-off-by: Andrii Kuiukoff <andros.ua@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20600
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The functions iterating through the port statistic/counter (for
initialization or polling) use the generic name "i" for the iterator. This
makes reading the actual body of the loop cumbersome because it is not
clear that various parameters of functions are about a ports.
Suggested-by: Felix Baumann <felix.bau@gmx.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Some SoC families require table access to get the HW counters. A mutex is
required for this access - which will potentially cause a sleep in the
current context. This is not always possible with .get_stats64 because it
is also called in atomic contexts.
For these SoCs, the retrieval of the current counters in .get_stats64 is
skipped and the counters are simply retrieved a lot more often from the HW.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
If an architecture doesn't need to sleep for retrieving the current
statistics from the HW, it is possible to directly retrieve the last values
from the HW when .get_stats64 is called. This avoids the stale counters
with the current refresh interval of 60 seconds.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
On many architectures, retrieving the HW counters from the switch is not
potentially sleeping. This would potentially allow these architectures to
retrieve the most recent values from the HW when .get_stats64 is called.
But because of the global mutex (which may sleep on lock), this would no
longer be possible.
Reintroduce the per port counters lock which protects from parallel
writes+reads of the non-link_stat counters. The locking is made abstract by
using helpers which identify the correct locking mechanism based on the
used read methods of the SoC.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add MIB data structures and table access routines for the RTL931X family.
These counters can now be exposed through the ethtool statistics interface.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Some Realtek SoCs such as the RTL931X store MIB counters in tables rather
than registers. Unlike register reads, table access requires programming
the table control register, setting the command field to determine read or
write, and then polling for completion. This makes it necessary to
implement a separate path for table-based statistics.
Like register-based MIBs, the table-based MIBs also come in two types: STD
and PRIV which will require slightly different implementations.
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Some Realtek SoCs do not expose MIB counters as simple registers. Instead,
retrieving counters may require blocking operations or take longer than a
normal register read. This makes the existing approach of direct reads
unsuitable. The existing approach uses spin locks which forbid sleeping
inside their context. But some hardware accesses methods (for example table
reads) might block (sleep).
To handle this, the MIB read path is redesigned with two levels of
locking:
* A global mutex protects updates of MIB data from the hardware. This is
necessary because reads can occur both in the polling workqueue and from
ethtool callbacks, also two user threads might call the ethtools
callbacks. A global mutex helps to avoid parallel reads of the same
hardware data. For table reads, this is not necessarily required because
they are already using a table lock. But they are the reason why
spin-locks can no longer be used (see above).
* A per-port spinlock protects the shared memory region where per-port
counters are copied. Avoids reading of half copied values in
.get_stats64()
As part of this change, MIB reads were removed from .get_stats64() since
that callback can be started from an atomic context and must never sleep
(block) in this context. A shared memory region is provided which will be
updated periodically by MIB workqueue and .get_stats64() will simply return
data from the shared memory.
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20631
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This PR fixes support for Cudy r700.
Original PR: https://github.com/openwrt/openwrt/pull/18532
Fixed:
- WAN port functionality;
- RESET button;
- Status LED;
- LAN port names consistent with the chassis;
- Merged partitions "debug", "backup" & "firmware" to one partition "firmware" ("debug" & "backup" contained unimportant data);
- Removed redundant DTS elements.
Installation:
To install OpenWRT, you need the intermediate firmware from Cudy. (U-boot is locked). After installing the intermediate firmware, you can install OpenWRT via sysupgrade.
Recovery:
TFTP available.
1. Place the recovery.bin in the serving directory of your TFTP server.
2. Set your IP to 192.168.1.88/24.
3. Press the “Reset” button of Cudy router and hold it. Before the Cudy router is powered on and before TFTP start to download the firmware, don't release the “Reset” button.
4. Power on the Cudy router.
5. You can release the reset button only when TFTP starts downloading firmware.
6. When the SYSTEM LED turns solid green, the upgrade is complete.
Fixes: 75403dd1d0 ("ramips: add support for Cudy R700")
Signed-off-by: Marcin Leksmark <lexmark3200@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/20756
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Hardware
--------
RockChip RK3528 ARM64 (4 cores)
1/2/4GB LPDDR4 RAM
1x LED (state)
1x Reset button
0/8/16/32/64GB eMMC on-board
Micro-SD Slot
PCIe FPC connector
3x USB 2.0 Port
HDMI/AV OUT
USB Type-C 5V Power
ROCK 2A:
+ 3.5mm audio out
+ 1000 Base-T
+ SYS LED
+ USB 3.0 Port (conflicts with PCIe)
Installation
------------
Uncompress the OpenWrt sysupgrade and write it to a micro SD card or
internal eMMC using dd.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/20375
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Unset KERNEL_LOADADDR in default profile to avoid using the value
from other boards (if someone forgets to set KERNEL_LOADADDR).
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/20375
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport pending nvmem/thermal/usb updates for rk3528.
These patches are not merged by upstream yet but worthy to have here.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/20375
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The probe order for PCIe buses and devices is non-deterministic,
making the names eth2 and eth3 unpredictable (they may be swapped).
This patch fixes the names by referencing the device path using
`ucidef_set_network_device_path`.
This patch ensures that the OpenWrt interface name matches the case label.
Fixes: 8ca4caacd0 ("rockchip: Add support for RK3568 LinkEase EasePi R1")
Signed-off-by: Liangbin Lian <jjm2473@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20779
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The MSTI range is 0..4095 but the HW range is only supporting a lower
range - for example 0..63 for RTL930x. But the HW doesn't really need to
know the actual MSTI. It is therefore possible to use a mapping from MSTI
to HW slot to allow a larger range of MSTIs.
Since the CIST (MSTI 0) is always needed, the mapping data structure is
skipping this entry and is always keeping the HW slot 0 for CIST.
This doesn't increase the total number of MSTIs a HW supports.
Suggested-by: Jonas Gorski <jonas.gorski@gmail.com>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The MSTP support (usually implemented by mstpd) requires from the kernel
that a VLAN can associated with an MSTI. At the moment, all these VLANs
just get the msti 0 harcoded on creation. But the
vlan_tables_read()+vlan_tables_write() helper already allow the
modification of the MSTI and only require a minimal hook to expose this
functionality.
It is also necessary to adjust the (M)STP states per MSTI and not only per
port (or for the CIST). The rtl83xx_port_stp_state_set() function was in
theory already capable to modify other MSTIs than CIST - if the msti would
not have been hardcoded to 0.
The userspace can trigger these modifications using netlink:
* (Re)associating VLANs with an MSTI:
bridge vlan global set dev <BR> vid <X> msti <Y>
* Setting the port state in a given MSTI:
bridge mst set dev <PORT> msti <Y> state <Z>
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The VLANs and their MSTIs are shared on the realtek switch HW between
bridged and unbridged ports. But the MSTI state cannot be updated for an
unbridged port via DSA. To ensure that the port is still configured
correctly after leaving a bridge, the CIST state updates via DSA must also
be propagated to the MSTI states.
Suggested-by: Jonas Gorski <jonas.gorski@gmail.com>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
When joining a bridge or leaving a bridge, the CIST state will
automatically be adjusted by DSA using .port_stp_state_set(). But MSTIs are
completely unhandled.
If a port is joining a bridge, the default state must be disabled. The MSTP
daemon is then responsible for adjusting the state.
If the bridge is left, the forwarding state must be enforced because VLANs
(and with this also the MSTIs assigned to them) are shared between bridged
and non-bridged ports. An unbridged port must therefore not be left in an
blocked/disabled state for a VLAN (MSTI).
Suggested-by: Jonas Gorski <jonas.gorski@gmail.com>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
If a VLAN doesn't have any members anymore, then it is removed and
implicitly returns back from any MSTI to CIST. The DSA layer will not
create any call to .vlan_msti_set and the driver is required to handle this
directly.
Suggested-by: Jonas Gorski <jonas.gorski@gmail.com>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Each SoC supports a different number of MST(I)s. The code must know this
limitation to correctly reject unsupported MSTIs or to allocate a large
enough mapping table.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The DSA port code is trying to flush associated VLANs whenever the MST
state is changed. This functionality is available on a per port+vid based
using the L2_TBL_FLUSH_CTRL which is already used for the .port_fast_age
callbacks.
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The realtek DSA switch driver sets up all VLANs using CIST. It is therefore
not necessary to enforce CIST using the ST_CTRL register.
This allows us later to overwrite the MSTI of VLANs. This is necessary to
get MSTP working on RTL93xx.
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20421
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This pull request is based on
- the discussions in https://forum.openwrt.org/t/adding-openwrt-support-for-linksys-mr6350
- https://github.com/openwrt/openwrt/pull/11405 which added support for similar devices.
Device Specs:
- IPQ4019
- Quad Core CPU
- 256 MB RAM
- 256 MB FLASH
- 4 LAN ports, 1 WAN port
- 2.4GHz (802.11n) and 5GHz (802.11c) wifi
- 3 LEDs (Red, blue, green) which are routed to one indicator at the top of the case
- 2 buttons (Reset, WPS)
Disassembling the device:
- There are 4 screws at the bottom of the device which must be removed
- Two are under the fron rubber feets
- Two are under the labels in the back (corner next to the rear rubber feets)
Serial interface:
- The serial interface is already populated on the device with a 6-pin header
- Pin 1 is next to the heatsink
- Pinout: 1: 3.3V, 2: TX, 3: RX, 4: unknown, 5: GND, 6: GND
- Settings: 115200, 8N1
Migrating to OpenWrt requires multiple steps:
- Load and boot the initramfs image
- Adapt U-Boot settings to support bigger kernels
- Flash the sysupgrade image
Load and boot initramfs:
- Connect serial interface
- Set up a TFTP server on IP 192.168.1.254
- Copy openwrt-ipq40xx-generic-linksys_mr6350-initramfs-zImage.itb to TFTP server
- Rename file to C0A80101.img
- Boot up the device and stop in U-Boot
- Run the following U-Boot commands after a link has been established:
tftp
bootm
- Initramfs image is started now.
Adapt U-Boot settings to support bigger kernels:
- Run "fw_printenv" in the initramfs image after booting
- There should be an entry kernsize=300000 which indicates the maximum size for the kernel is 3MB
- Execute "fw_setenv kernsize 500000" to increase the max kernel size to 5MB
- Check that the change are applied with "fw_printenv"
Flash the sysupgrade image:
- Default sysupgrade routine either with a initramfs image containing LuCI or via command line.
Revert back to OEM firmware:
- Only tested with FW_MR6350_1.1.3.210129_prod.img
- Flash the OEM firmware via sysupgrade
- Forced update is required
Signed-off-by: Roland Reinl <reinlroland+github@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17977
Signed-off-by: Robert Marko <robimarko@gmail.com>
This device has only half the flash and ram of the RBR20. It also has
two lan ports instead of wan and lan.
Hardware
--------
SOC: Qualcomm IPQ4019
FLASH: 128MB (Winbond W29N01HVSINF)
RAM: 256MB (Winbond W632GU6MB-12)
WIFI: Qualcomm IPQ4019
Qualcomm Atheros QCA9886
ETH: 2x LAN
LED: 5 (4 RGB at top, 1 RG at back)
BTN: WPS, Reset
UART: 115200 8N1 (dotted Pin = VCC) VCC-TX-RX-GND
MAC addresses
-------------
LAN Label MAC (stored in boarddata1 offset 0x0)
2.4G LAN
5GLow LAN + 3 (stored in boarddata1 offset 0xc)
5GUpper LAN + 2 (stored in boarddata1 offset 0x12)
Installation
------------
Either use the vendor ui upgrade method or nmrpflash to install the
factory image.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20560
Signed-off-by: Robert Marko <robimarko@gmail.com>
This device shares a lot of similarities with the LBR20 - the RBR20 just
misses the LTE modem and its formfactor is alot smaller. Other than that
the LED configuration matches other RBR devices but the RBR20 has less
LEDs than its larger counterparts.
Hardware
--------
SOC: Qualcomm IPQ4019
FLASH: 256MB (Winbond W29N02GVSIAF)
RAM: 512MB (Nanya NT5CC256M16EP-EK)
WIFI: Qualcomm IPQ4019
Qualcomm Atheros QCA9886
ETH: 1x WAN, 1x LAN
LED: 5 (4 RGB at top, 1 RG at back)
BTN: WPS, Reset
UART: 115200 8N1 (dotted Pin = VCC) VCC-TX-RX-GND
MAC addresses
-------------
LAN Label MAC (stored in boarddata1 offset 0x0)
WAN LAN + 1 (stored in boarddata1 offset 0x6)
2.4G LAN
5GLow LAN + 3 (stored in boarddata1 offset 0xc)
5GUpper LAN + 2 (stored in boarddata1 offset 0x12)
Installation
------------
Either use the vendor ui upgrade method or nmrpflash to install the
factory image.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20560
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL838x+RTL839x both configure a default QoS behavior with a default
mapping. This also needs to be added to RTL93xx to ensure a consistent
behavior:
* Set the default mapping between DSCP and priority: prio = dscp >> 3.
* Set the default mapping between internal priority and queues
* Set uniform prioritization of queues (as with other SoCs)
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20640
Signed-off-by: Robert Marko <robimarko@gmail.com>
If link aggregation with LACP is activated, we must send out the LACP
packets on the physical port and not on a logic port. Otherwise, the per
port packets might be (rebalanced) between the different ports in a link
aggregation group.
Such rebalancing breaks 802.3ad and will leave ports in a churned state.
Fixes: 8c42e63a69 ("realtek: rtl93xx: fix incorrect destination port selection")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20728
Signed-off-by: Robert Marko <robimarko@gmail.com>
If ports of a RTL93xx switch are not added to a port matrix then they are
not used for the link aggregation. As result, communication will then just
break on non-primary interfaces.
This can be reproduced in balanced-xor and 802.3ad bandwidth mode.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20729
Signed-off-by: Robert Marko <robimarko@gmail.com>
Commit 56e9a73d0b added support for configuring the SerDes polarity for
both RTL930X and RTL931X. Based on the code in the Realtek SDK in [1]
and [2], in both cases the same register bits are set. Thus, a common
implementation was provided which worked with e.g. USXGMII or 10GBase-R
configured SerDes.
However, after further tests, a strange issue occured where it didn't
work that well for all SerDes configurations. While running fine for
10GBase-R links on two adjacent SerDes, it didn't for 1000Base-X links
on one of two adjacent SerDes with the link not being detected as a
symptom.
Diving into the SDK again revealed that the referenced implementation of
polarity configuration is (by accident or by purpose) misleading. While
[1] and [3] for RTL930X match, [2] and [4] for RTL931X actually don't.
[4] writes the bits for the 1G polarity setting on different background
SerDes, thus in another frontend page.
Split implementations for RTL930X and RTL931X again and adjust the one
for RTL931X according to [4]. This resolves the issues with 1000Base-X
behavior.
[1] 69d2890a2e/sources/rtk-xgs1210/src/hal/phy/phy_rtl9300.c (L1384)
[2] 69d2890a2e/sources/rtk-xgs1210/src/hal/phy/phy_rtl9310.c (L3479)
[3] 69d2890a2e/sources/rtk-xgs1210/src/dal/longan/dal_longan_construct.c (L2246)
[4] 69d2890a2e/sources/rtk-xgs1210/src/dal/mango/dal_mango_construct.c (L1550)
Fixes: 56e9a73d0b ("realtek: pcs: rtl93xx: provide proper SerDes polarity
configuration")
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20767
Signed-off-by: Robert Marko <robimarko@gmail.com>
The MikroTik RouterBOARD 962UiGS-5HacT2HnT (hAP ac) currently comes up
with random MAC addresses. Assign the MAC addresses from hard_config for
LAN and WAN ports.
Fixes: c2140e32ce ("ath79: add support for MikroTik RouterBOARD 962UiGS-5HacT2HnT (hAP ac)")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://github.com/openwrt/openwrt/pull/20782
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add mt7987-2p5g-phy-firmware to DEVICES_PACKAGES of the MT7987A RFB as
well as the BananaPi R4 Lite.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Use skb->encapsulation flag instead of skb_tnl_header_len() to detect
encapsulated packets. Prevents false positives on non-encapsulated packets.
Reported-by: Mason-cw Chang (張哲維) <Mason-cw.Chang@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Usage of strlcpy results in a compilation error. strscpy is preferred
anyways and equivalent for our case.
Signed-off-by: David Bauer <mail@david-bauer.net>
This is an automatically generated commit which aids following Kernel patch
history, as git will see the move and copy as a rename thus defeating the
purpose.
For the original discussion see:
https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
This is an automatically generated commit.
When doing `git bisect`, consider `git bisect --skip`.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
CMCC PZ-L8 is a 2.4/5 GHz band 11ax (Wi-Fi 6) router, based on IPQ5000.
Specifications:
- SoC : Qualcomm IPQ5000
- RAM : Integrated 256MiB DDR3L
- Flash : 128 MiB SPI-NAND (ESMT F50D1G41LB)
- WLAN : 2.4/5 GHz 2T2R
- 2.4 GHz : Qualcomm IPQ5000 (SoC)
- 5 GHz : Qualcomm Atheros QCN6102
- Ethernet : 4x 10/100/1000 Mbps
- switch : Qualcomm Atheros QCA8337
- LEDs/Keys (GPIO) : 2x LEDs, 2x Keys
- UART : Through-hole on PCB, 4pins in the middle of the black aluminum heat sink
- assignment : 3.3V, GND,TX, RX (from left to right)
- settings : 115200n8
- Power : 12 VDC, 1 A
Flashing Instructions:
1. SSH Method
(1) Enable SSH on the stock firmware
a. Version 501.8 and 501.9:
Log in to http://192.168.10.1 with the password on the sticker
Append "/admin/system/admin" to the URL and press Enter
Delete "Dropbear instance", click "Add instance", then "Save and Apply"
Reboot the router
b. Version 501.11 and 501.12:
While the router is running the stock firmware, press and hold the reset button for 20-30 seconds
Open http://192.168.10.1:56781 and login with username "root" and the password on the sticker
Run "vi /etc/config/dropbear" and delete the line "option enable '0'"
Reboot the router
(2) Upload the factory.ubi file to router's /tmp directory (using scp or wget)
and execute the following commands in the router's shell
export rootfs=$(cat /proc/mtd | grep rootfs | grep -v _ | cut -d: -f1)
ubidetach -f -p /dev/${rootfs}
ubiformat /dev/${rootfs} -y -f /tmp/factory.ubi
2. U-Boot Method using UBI Image
Place the factory.ubi file on your TFTP server, enter U-Boot CLI and exec these commands
tftpboot <your_tftp_server_ip>:factory.ubi
flash rootfs
reset
3. U-Boot Method using initramfs Image
(1) Place the openwrt-*-initramfs-fit-uImage.itb file on your TFTP server
and rename it to initramfs.bin
(2) Enable serial console, enter to U-Boot CLI and exec these commands
tftpboot <your_tftp_server_ip>:initramfs.bin
bootm
(3) Once boot completed, upload the sysupgrade.bin file to router's /tmp directory
(using scp or wget) and execute the following command in openwrt shell
sysupgrade -n /tmp/sysupgrade.bin
Switching to the Stock Firmware:
Please follow the commit 3b7d72bc2e
Partition Layout (Stock Firmware):
0x000000000000-0x000000080000 : "0:SBL1"
0x000000080000-0x000000100000 : "0:MIBIB"
0x000000100000-0x000000140000 : "0:BOOTCONFIG"
0x000000140000-0x000000180000 : "0:BOOTCONFIG1"
0x000000180000-0x000000280000 : "0:QSEE"
0x000000280000-0x000000380000 : "0:QSEE_1"
0x000000380000-0x0000003c0000 : "0:DEVCFG"
0x0000003c0000-0x000000400000 : "0:DEVCFG_1"
0x000000400000-0x000000440000 : "0:CDT"
0x000000440000-0x000000480000 : "0:CDT_1"
0x000000480000-0x000000500000 : "0:APPSBLENV"
0x000000500000-0x000000640000 : "0:APPSBL"
0x000000640000-0x000000780000 : "0:APPSBL_1"
0x000000780000-0x000000880000 : "0:ART"
0x000000880000-0x000000900000 : "0:TRAINING"
0x000000900000-0x000004300000 : "rootfs"
0x000004300000-0x000007d00000 : "rootfs_1"
Notes:
This device is almost the same as ELECOM WRC-X3000GS2, including partition layout and the dual-boot feature.
Known Issues:
- All Wi-Fi related peripherals are disabled in device tree, since 256 MiB RAM is too few for ath11k.
- This device has another version with nand flash FM25SL01, which is not supported at the moment.
https://github.com/immortalwrt/immortalwrt/blob/master/target/linux/mediatek/patches-6.12/342-mtd-spinand-Support-fmsh.patch
MAC Addresses:
Interface MAC Address Location (binary)
LAN A4:39:B6:xx:xx:9D (0:ART, 0x00-0x05)
WAN A4:39:B6:xx:xx:9E (0:ART, 0x06-0x0B)
2.4 GHz A4:39:B6:xx:xx:9F (0:ART, 0x0C-0x11)
5 GHz A4:39:B6:xx:xx:A0 (0:ART, 0x12-0x17)
Signed-off-by: Chang Liu <jssqliuchang@gmail.com>
The "old" QCA8084 PHY driver does not implement 10g-qxgmii support.
This is blocking several devices which use the QCA8084 form being
merged. Qualcomm has provided updated drivers for the MAC (ppe), PCS,
and PHY via github. We only need to update the PHY driver.
Update the QCA8084 PHY driver using the patches provided by Qualcomm.
Re-organize the patches so that the changes go into the existing
patches. The SERDES functionality is new, so it gets new patches. This
is sufficient to enable 10g-qxgmii on ipq95xx platforms.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20721
Signed-off-by: Robert Marko <robimarko@gmail.com>
Replace Airoha AN7583 pinctrl patch with upstream version as it has been
accepted upstream. Add the related kernel version tag to identify it.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The unit-address of the ubi partition was @a9c0000 but the partition
actually starts at offset 0x0ad00000. Ideally they should match, so
align them.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20733
Signed-off-by: Robert Marko <robimarko@gmail.com>
The name "is_lagmember" implies that the port is part of a LAG. But this
information is already stored in lagmembers. In reality, it is stored the
non-primary LAG members. Renaming it accordingly, makes the code a lot more
readable
Also the type (u32 array) looks like it would contain some kind of large id
(like the group ID). But it only stores a single bit. It is more appropriate
to just use a single bit per port.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20707
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
