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rockchip: backport dts updates for rk3528

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Backport core dts updates for rk3528.

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/20375
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Tianling Shen 2025-10-11 17:04:07 +08:00 • committed by Hauke Mehrtens
parent c7a26da60d
commit 97b90c5951
26 changed files with 4142 additions and 0 deletions
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210
target/linux/rockchip/patches-6.12/070-01-v6.13-arm64-dts-rockchip-Add-base-DT-for-rk3528-SoC.patch Normal file
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@ -0,0 +1,210 @@
From 7983e6c379a917c500eff31f5f9c646cc408e030 Mon Sep 17 00:00:00 2001
From: Yao Zi <ziyao@disroot.org>
Date: Thu, 29 Aug 2024 09:27:04 +0000
Subject: [PATCH] arm64: dts: rockchip: Add base DT for rk3528 SoC
This initial device tree describes CPU, interrupts and UART on the chip
and is able to boot into basic kernel with only UART. Cache information
is omitted for now as there is no precise documentation. Support for
other features will be added later.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20240829092705.6241-4-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 189 +++++++++++++++++++++++
1 file changed, 189 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3528.dtsi
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "rockchip,rk3528";
+
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ xin24m: clock-xin24m {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ gic: interrupt-controller@fed01000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xfed01000 0 0x1000>,
+ <0x0 0xfed02000 0 0x2000>,
+ <0x0 0xfed04000 0 0x2000>,
+ <0x0 0xfed06000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <3>;
+ };
+
+ uart0: serial@ff9f0000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff9f0000 0x0 0x100>;
+ clock-frequency = <24000000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart1: serial@ff9f8000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff9f8000 0x0 0x100>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart2: serial@ffa00000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa00000 0x0 0x100>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart3: serial@ffa08000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa08000 0x0 0x100>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart4: serial@ffa10000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa10000 0x0 0x100>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart5: serial@ffa18000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa18000 0x0 0x100>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart6: serial@ffa20000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa20000 0x0 0x100>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart7: serial@ffa28000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa28000 0x0 0x100>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+ };
+};

90
target/linux/rockchip/patches-6.12/070-02-v6.15-arm64-dts-rockchip-Add-clock-generators-for-RK3528-SoC.patch Normal file
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From 858cdcdd11cf9913756297d3869e4de0f01329ea Mon Sep 17 00:00:00 2001
From: Yao Zi <ziyao@disroot.org>
Date: Mon, 17 Feb 2025 06:11:45 +0000
Subject: [PATCH] arm64: dts: rockchip: Add clock generators for RK3528 SoC
Add dt node for RK3528 clock and reset unit. Clock "gmac0_clk" is
generated by internal Ethernet phy, a fixed clock node is added as a
placeholder to avoid orphans.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20250217061142.38480-9-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 51 ++++++++++++++++++++++++
1 file changed, 51 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/rockchip,rk3528-cru.h>
/ {
compatible = "rockchip,rk3528";
@@ -95,6 +96,13 @@
#clock-cells = <0>;
};
+ gmac0_clk: clock-gmac50m {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "gmac0";
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
@@ -114,6 +122,49 @@
#interrupt-cells = <3>;
};
+ cru: clock-controller@ff4a0000 {
+ compatible = "rockchip,rk3528-cru";
+ reg = <0x0 0xff4a0000 0x0 0x30000>;
+ assigned-clocks =
+ <&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>,
+ <&cru PLL_PPLL>, <&cru PLL_CPLL>,
+ <&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>,
+ <&cru CLK_MATRIX_500M_SRC>,
+ <&cru CLK_MATRIX_50M_SRC>,
+ <&cru CLK_MATRIX_100M_SRC>,
+ <&cru CLK_MATRIX_150M_SRC>,
+ <&cru CLK_MATRIX_200M_SRC>,
+ <&cru CLK_MATRIX_300M_SRC>,
+ <&cru CLK_MATRIX_339M_SRC>,
+ <&cru CLK_MATRIX_400M_SRC>,
+ <&cru CLK_MATRIX_600M_SRC>,
+ <&cru CLK_PPLL_50M_MATRIX>,
+ <&cru CLK_PPLL_100M_MATRIX>,
+ <&cru CLK_PPLL_125M_MATRIX>,
+ <&cru ACLK_BUS_VOPGL_ROOT>;
+ assigned-clock-rates =
+ <32768>, <1188000000>,
+ <1000000000>, <996000000>,
+ <408000000>, <250000000>,
+ <500000000>,
+ <50000000>,
+ <100000000>,
+ <150000000>,
+ <200000000>,
+ <300000000>,
+ <340000000>,
+ <400000000>,
+ <600000000>,
+ <50000000>,
+ <100000000>,
+ <125000000>,
+ <500000000>;
+ clocks = <&xin24m>, <&gmac0_clk>;
+ clock-names = "xin24m", "gmac0";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
uart0: serial@ff9f0000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xff9f0000 0x0 0x100>;

89
target/linux/rockchip/patches-6.12/070-03-v6.15-arm64-dts-rockchip-Add-UART-clocks-for-RK3528-SoC.patch Normal file
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From b9454434d0349223418f74fbfa7b902104da9bc5 Mon Sep 17 00:00:00 2001
From: Yao Zi <ziyao@disroot.org>
Date: Mon, 17 Feb 2025 06:11:46 +0000
Subject: [PATCH] arm64: dts: rockchip: Add UART clocks for RK3528 SoC
Add missing clocks in UART nodes for RK3528 SoC.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20250217061142.38480-10-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -168,7 +168,8 @@
uart0: serial@ff9f0000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xff9f0000 0x0 0x100>;
- clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -178,6 +179,8 @@
uart1: serial@ff9f8000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xff9f8000 0x0 0x100>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -187,6 +190,8 @@
uart2: serial@ffa00000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa00000 0x0 0x100>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -195,6 +200,8 @@
uart3: serial@ffa08000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
reg = <0x0 0xffa08000 0x0 0x100>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -204,6 +211,8 @@
uart4: serial@ffa10000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa10000 0x0 0x100>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -213,6 +222,8 @@
uart5: serial@ffa18000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa18000 0x0 0x100>;
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -222,6 +233,8 @@
uart6: serial@ffa20000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa20000 0x0 0x100>;
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -231,6 +244,8 @@
uart7: serial@ffa28000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa28000 0x0 0x100>;
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;

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target/linux/rockchip/patches-6.12/070-04-v6.15-arm64-dts-rockchip-Add-pinctrl-and-gpio-nodes-for-RK3528.patch Normal file
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target/linux/rockchip/patches-6.12/070-05-v6.15-arm64-dts-rockchip-Add-rk3528-QoS-register-node.patch Normal file
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@ -0,0 +1,185 @@
From 61a05d8ca3030a544175671f5fab7a8f29c24085 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Thu, 6 Mar 2025 20:38:09 +0800
Subject: [PATCH] arm64: dts: rockchip: Add rk3528 QoS register node
The Quality-of-Service (QsS) node stores/restores specific
register contents when the power domains is turned off/on.
Add QoS node so that they can connect to the power domain.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20250306123809.273655-3-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 160 +++++++++++++++++++++++
1 file changed, 160 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -129,6 +129,166 @@
#interrupt-cells = <3>;
};
+ qos_crypto_a: qos@ff200000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200000 0x0 0x20>;
+ };
+
+ qos_crypto_p: qos@ff200080 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200080 0x0 0x20>;
+ };
+
+ qos_dcf: qos@ff200100 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200100 0x0 0x20>;
+ };
+
+ qos_dft2apb: qos@ff200200 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200200 0x0 0x20>;
+ };
+
+ qos_dma2ddr: qos@ff200280 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200280 0x0 0x20>;
+ };
+
+ qos_dmac: qos@ff200300 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200300 0x0 0x20>;
+ };
+
+ qos_keyreader: qos@ff200380 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200380 0x0 0x20>;
+ };
+
+ qos_cpu: qos@ff210000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff210000 0x0 0x20>;
+ };
+
+ qos_debug: qos@ff210080 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff210080 0x0 0x20>;
+ };
+
+ qos_gpu_m0: qos@ff220000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff220000 0x0 0x20>;
+ };
+
+ qos_gpu_m1: qos@ff220080 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff220080 0x0 0x20>;
+ };
+
+ qos_pmu_mcu: qos@ff240000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff240000 0x0 0x20>;
+ };
+
+ qos_rkvdec: qos@ff250000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff250000 0x0 0x20>;
+ };
+
+ qos_rkvenc: qos@ff260000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff260000 0x0 0x20>;
+ };
+
+ qos_gmac0: qos@ff270000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270000 0x0 0x20>;
+ };
+
+ qos_hdcp: qos@ff270080 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270080 0x0 0x20>;
+ };
+
+ qos_jpegdec: qos@ff270100 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270100 0x0 0x20>;
+ };
+
+ qos_rga2_m0ro: qos@ff270200 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270200 0x0 0x20>;
+ };
+
+ qos_rga2_m0wo: qos@ff270280 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270280 0x0 0x20>;
+ };
+
+ qos_sdmmc0: qos@ff270300 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270300 0x0 0x20>;
+ };
+
+ qos_usb2host: qos@ff270380 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270380 0x0 0x20>;
+ };
+
+ qos_vdpp: qos@ff270480 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270480 0x0 0x20>;
+ };
+
+ qos_vop: qos@ff270500 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270500 0x0 0x20>;
+ };
+
+ qos_emmc: qos@ff280000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280000 0x0 0x20>;
+ };
+
+ qos_fspi: qos@ff280080 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280080 0x0 0x20>;
+ };
+
+ qos_gmac1: qos@ff280100 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280100 0x0 0x20>;
+ };
+
+ qos_pcie: qos@ff280180 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280180 0x0 0x20>;
+ };
+
+ qos_sdio0: qos@ff280200 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280200 0x0 0x20>;
+ };
+
+ qos_sdio1: qos@ff280280 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280280 0x0 0x20>;
+ };
+
+ qos_tsp: qos@ff280300 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280300 0x0 0x20>;
+ };
+
+ qos_usb3otg: qos@ff280380 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280380 0x0 0x20>;
+ };
+
+ qos_vpu: qos@ff280400 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280400 0x0 0x20>;
+ };
+
cru: clock-controller@ff4a0000 {
compatible = "rockchip,rk3528-cru";
reg = <0x0 0xff4a0000 0x0 0x30000>;

83
target/linux/rockchip/patches-6.12/070-06-v6.15-arm64-dts-rockchip-enable-SCMI-clk-for-RK3528-SoC.patch Normal file
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@ -0,0 +1,83 @@
From fbcbc1fb93e14729bd87ab386b7f62694dcc8b51 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Fri, 7 Mar 2025 18:00:08 +0800
Subject: [PATCH] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC
Same as RK3568, RK3528 uses SCMI clk instead of ARMCLK.
Add SCMI clk for CPU, GPU and RNG will also use it.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20250307100008.789129-2-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 31 ++++++++++++++++++++++++
1 file changed, 31 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -59,6 +59,7 @@
reg = <0x0>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
};
cpu1: cpu@1 {
@@ -66,6 +67,7 @@
reg = <0x1>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
};
cpu2: cpu@2 {
@@ -73,6 +75,7 @@
reg = <0x2>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
};
cpu3: cpu@3 {
@@ -80,6 +83,22 @@
reg = <0x3>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
+ };
+ };
+
+ firmware {
+ scmi: scmi {
+ compatible = "arm,scmi-smc";
+ arm,smc-id = <0x82000010>;
+ shmem = <&scmi_shmem>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
};
};
@@ -88,6 +107,18 @@
method = "smc";
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ scmi_shmem: shmem@10f000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x0010f000 0x0 0x100>;
+ no-map;
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

43
target/linux/rockchip/patches-6.12/070-07-v6.15-arm64-dts-rockchip-Add-SARADC-node-for-RK3528.patch Normal file
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@ -0,0 +1,43 @@
From 6e58302c84ce90aadbecd41efe1f69098a6f91e5 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Tue, 4 Mar 2025 20:16:36 +0000
Subject: [PATCH] arm64: dts: rockchip: Add SARADC node for RK3528
Add a device tree node for the SARADC controller used by RK3528.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250304201642.831218-4-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rockchip,rk3528-cru.h>
+#include <dt-bindings/reset/rockchip,rk3528-cru.h>
/ {
compatible = "rockchip,rk3528";
@@ -455,6 +456,18 @@
status = "disabled";
};
+ saradc: adc@ffae0000 {
+ compatible = "rockchip,rk3528-saradc";
+ reg = <0x0 0xffae0000 0x0 0x10000>;
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cru SRST_P_SARADC>;
+ reset-names = "saradc-apb";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3528-pinctrl";
rockchip,grf = <&ioc_grf>;

50
target/linux/rockchip/patches-6.12/070-08-v6.15-arm64-dts-rockchip-Add-SDHCI-controller-for-RK3528.patch Normal file
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@ -0,0 +1,50 @@
From a98cc47f79ab5b8059b748bf0bd59335edfff7d9 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 5 Mar 2025 21:41:03 +0000
Subject: [PATCH] arm64: dts: rockchip: Add SDHCI controller for RK3528
The SDHCI controller in Rockchip RK3528 is similar to the one included
in RK3588.
Add device tree node for the SDHCI controller in RK3528.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250305214108.1327208-3-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -468,6 +468,30 @@
status = "disabled";
};
+ sdhci: mmc@ffbf0000 {
+ compatible = "rockchip,rk3528-dwcmshc",
+ "rockchip,rk3588-dwcmshc";
+ reg = <0x0 0xffbf0000 0x0 0x10000>;
+ assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
+ <&cru CCLK_SRC_EMMC>;
+ assigned-clock-rates = <200000000>, <24000000>,
+ <200000000>;
+ clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
+ <&cru TCLK_EMMC>;
+ clock-names = "core", "bus", "axi", "block", "timer";
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
+ <&emmc_strb>;
+ resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
+ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
+ <&cru SRST_T_EMMC>;
+ reset-names = "core", "bus", "axi", "block", "timer";
+ status = "disabled";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3528-pinctrl";
rockchip,grf = <&ioc_grf>;

30
target/linux/rockchip/patches-6.12/070-09-v6.16-arm64-dts-rockchip-Add-missing-uart3-interrupt-for-RK3528.patch Normal file
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@ -0,0 +1,30 @@
From a37d21a9b45e47ed6bc1f94e738096c07db78a07 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Tue, 1 Apr 2025 18:00:18 +0800
Subject: [PATCH] arm64: dts: rockchip: Add missing uart3 interrupt for RK3528
The interrupt of uart3 node on rk3528 is missing, fix it.
Fixes: 7983e6c379a9 ("arm64: dts: rockchip: Add base DT for rk3528 SoC")
Reviewed-by: Yao Zi <ziyao@disroot.org>
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20250401100020.944658-2-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -404,9 +404,10 @@
uart3: serial@ffa08000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa08000 0x0 0x100>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
- reg = <0x0 0xffa08000 0x0 0x100>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";

41
target/linux/rockchip/patches-6.12/070-10-v6.16-arm64-dts-rockchip-Add-DMA-controller-for-RK3528.patch Normal file
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@ -0,0 +1,41 @@
From 762b1f6503340b4729bc8a5fa6a5780712012cd8 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Tue, 1 Apr 2025 18:00:19 +0800
Subject: [PATCH] arm64: dts: rockchip: Add DMA controller for RK3528
Add DMA controller dt node for RK3528 SoC.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20250401100020.944658-3-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -493,6 +493,24 @@
status = "disabled";
};
+ dmac: dma-controller@ffd60000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xffd60000 0x0 0x4000>;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ arm,pl330-periph-burst;
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3528-pinctrl";
rockchip,grf = <&ioc_grf>;

81
target/linux/rockchip/patches-6.12/070-11-v6.16-arm64-dts-rockchip-Add-UART-DMA-support-for-RK3528.patch Normal file
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@ -0,0 +1,81 @@
From ab6fcb58aedf7df1d146b47d5fedd844a7c346e2 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Tue, 1 Apr 2025 18:00:20 +0800
Subject: [PATCH] arm64: dts: rockchip: Add UART DMA support for RK3528
The UART ports on RK3528 have DMA capability, describe it.
Flow control is optional, so dma-names are not added.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20250401100020.944658-4-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -375,6 +375,7 @@
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 8>, <&dmac 9>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -386,6 +387,7 @@
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 10>, <&dmac 11>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -397,6 +399,7 @@
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 12>, <&dmac 13>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -408,6 +411,7 @@
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 14>, <&dmac 15>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -419,6 +423,7 @@
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 16>, <&dmac 17>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -430,6 +435,7 @@
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 18>, <&dmac 19>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -441,6 +447,7 @@
clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 20>, <&dmac 21>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -452,6 +459,7 @@
clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 22>, <&dmac 23>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";

143
target/linux/rockchip/patches-6.12/070-12-v6.16-arm64-dts-rockchip-Add-I2C-controllers-for-RK3528.patch Normal file
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@ -0,0 +1,143 @@
From d3a05f490d048808968df1e0d3240ab01fe82211 Mon Sep 17 00:00:00 2001
From: Yao Zi <ziyao@disroot.org>
Date: Thu, 17 Apr 2025 12:01:18 +0000
Subject: [PATCH] arm64: dts: rockchip: Add I2C controllers for RK3528
Describe I2C controllers shipped by RK3528 in devicetree. For I2C-2,
I2C-4 and I2C-7 which come with only a set of possible pins, a default
pin configuration is included.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250417120118.17610-5-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 110 +++++++++++++++++++++++
1 file changed, 110 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -24,6 +24,14 @@
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -465,6 +473,108 @@
status = "disabled";
};
+ i2c0: i2c@ffa50000 {
+ compatible = "rockchip,rk3528-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa50000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@ffa58000 {
+ compatible = "rockchip,rk3528-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa58000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@ffa60000 {
+ compatible = "rockchip,rk3528-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa60000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2m1_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@ffa68000 {
+ compatible = "rockchip,rk3528-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa68000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@ffa70000 {
+ compatible = "rockchip,rk3528-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa70000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@ffa78000 {
+ compatible = "rockchip,rk3528-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa78000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@ffa80000 {
+ compatible = "rockchip,rk3528-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa80000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@ffa88000 {
+ compatible = "rockchip,rk3528-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa88000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
saradc: adc@ffae0000 {
compatible = "rockchip,rk3528-saradc";
reg = <0x0 0xffae0000 0x0 0x10000>;

105
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@ -0,0 +1,105 @@
From 9e701ad7c3551b3ab87ed5fa439569696ddf42e4 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Tue, 1 Apr 2025 20:00:19 +0800
Subject: [PATCH] arm64: dts: rockchip: Add pwm nodes for RK3528
Add pwm nodes for RK3528. The PWM core on RK3528 is the same as
RK3328, but the driver does not support interrupts yet.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250401120020.976343-2-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 80 ++++++++++++++++++++++++
1 file changed, 80 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -575,6 +575,86 @@
status = "disabled";
};
+ pwm0: pwm@ffa90000 {
+ compatible = "rockchip,rk3528-pwm",
+ "rockchip,rk3328-pwm";
+ reg = <0x0 0xffa90000 0x0 0x10>;
+ clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
+ clock-names = "pwm", "pclk";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@ffa90010 {
+ compatible = "rockchip,rk3528-pwm",
+ "rockchip,rk3328-pwm";
+ reg = <0x0 0xffa90010 0x0 0x10>;
+ clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
+ clock-names = "pwm", "pclk";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@ffa90020 {
+ compatible = "rockchip,rk3528-pwm",
+ "rockchip,rk3328-pwm";
+ reg = <0x0 0xffa90020 0x0 0x10>;
+ clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
+ clock-names = "pwm", "pclk";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@ffa90030 {
+ compatible = "rockchip,rk3528-pwm",
+ "rockchip,rk3328-pwm";
+ reg = <0x0 0xffa90030 0x0 0x10>;
+ clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
+ clock-names = "pwm", "pclk";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@ffa98000 {
+ compatible = "rockchip,rk3528-pwm",
+ "rockchip,rk3328-pwm";
+ reg = <0x0 0xffa98000 0x0 0x10>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@ffa98010 {
+ compatible = "rockchip,rk3528-pwm",
+ "rockchip,rk3328-pwm";
+ reg = <0x0 0xffa98010 0x0 0x10>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@ffa98020 {
+ compatible = "rockchip,rk3528-pwm",
+ "rockchip,rk3328-pwm";
+ reg = <0x0 0xffa98020 0x0 0x10>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm7: pwm@ffa98030 {
+ compatible = "rockchip,rk3528-pwm",
+ "rockchip,rk3328-pwm";
+ reg = <0x0 0xffa98030 0x0 0x10>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
saradc: adc@ffae0000 {
compatible = "rockchip,rk3528-saradc";
reg = <0x0 0xffae0000 0x0 0x10000>;

103
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@ -0,0 +1,103 @@
From 894a2640422208b1d3e4c238f126220d406e5fb1 Mon Sep 17 00:00:00 2001
From: Yao Zi <ziyao@disroot.org>
Date: Thu, 8 May 2025 23:48:29 +0000
Subject: [PATCH] arm64: dts: rockchip: Add SDMMC/SDIO controllers for RK3528
RK3528 features two SDIO controllers and one SD/MMC controller, describe
them in devicetree. Since their sample and drive clocks are located in
the VO and VPU GRFs, corresponding syscons are added to make these
clocks available.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250508234829.27111-3-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 69 ++++++++++++++++++++++++
1 file changed, 69 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -329,6 +329,16 @@
reg = <0x0 0xff280400 0x0 0x20>;
};
+ vpu_grf: syscon@ff340000 {
+ compatible = "rockchip,rk3528-vpu-grf", "syscon";
+ reg = <0x0 0xff340000 0x0 0x8000>;
+ };
+
+ vo_grf: syscon@ff360000 {
+ compatible = "rockchip,rk3528-vo-grf", "syscon";
+ reg = <0x0 0xff360000 0x0 0x10000>;
+ };
+
cru: clock-controller@ff4a0000 {
compatible = "rockchip,rk3528-cru";
reg = <0x0 0xff4a0000 0x0 0x30000>;
@@ -691,6 +701,65 @@
status = "disabled";
};
+ sdio0: mmc@ffc10000 {
+ compatible = "rockchip,rk3528-dw-mshc",
+ "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xffc10000 0x0 0x4000>;
+ clocks = <&cru HCLK_SDIO0>,
+ <&cru CCLK_SRC_SDIO0>,
+ <&cru SCLK_SDIO0_DRV>,
+ <&cru SCLK_SDIO0_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>;
+ resets = <&cru SRST_H_SDIO0>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ sdio1: mmc@ffc20000 {
+ compatible = "rockchip,rk3528-dw-mshc",
+ "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xffc20000 0x0 0x4000>;
+ clocks = <&cru HCLK_SDIO1>,
+ <&cru CCLK_SRC_SDIO1>,
+ <&cru SCLK_SDIO1_DRV>,
+ <&cru SCLK_SDIO1_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>;
+ resets = <&cru SRST_H_SDIO1>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ sdmmc: mmc@ffc30000 {
+ compatible = "rockchip,rk3528-dw-mshc",
+ "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xffc30000 0x0 0x4000>;
+ clocks = <&cru HCLK_SDMMC0>,
+ <&cru CCLK_SRC_SDMMC0>,
+ <&cru SCLK_SDMMC_DRV>,
+ <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>,
+ <&sdmmc_det>;
+ resets = <&cru SRST_H_SDMMC0>;
+ reset-names = "reset";
+ rockchip,default-sample-phase = <90>;
+ status = "disabled";
+ };
+
dmac: dma-controller@ffd60000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xffd60000 0x0 0x4000>;

132
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@ -0,0 +1,132 @@
From 5eb28f461a1b368a57994cc3b3f2ba3154c00bb8 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Fri, 9 May 2025 20:23:57 +0000
Subject: [PATCH] arm64: dts: rockchip: Add GMAC nodes for RK3528
Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC
Ethernet QoS IP.
Add device tree nodes for the two Ethernet controllers in RK3528.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Tested-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20250509202402.260038-2-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 105 +++++++++++++++++++++++
1 file changed, 105 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -677,6 +677,111 @@
status = "disabled";
};
+ gmac0: ethernet@ffbd0000 {
+ compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0xffbd0000 0x0 0x10000>;
+ clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>,
+ <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>,
+ <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>;
+ clock-names = "stmmaceth", "clk_mac_ref",
+ "mac_clk_rx", "mac_clk_tx",
+ "pclk_mac", "aclk_mac";
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ phy-handle = <&rmii0_phy>;
+ phy-mode = "rmii";
+ resets = <&cru SRST_A_MAC_VO>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&vo_grf>;
+ snps,axi-config = <&gmac0_stmmac_axi_setup>;
+ snps,mixed-burst;
+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
+ snps,tso;
+ status = "disabled";
+
+ mdio0: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ rmii0_phy: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x2>;
+ clocks = <&cru CLK_MACPHY>;
+ phy-is-integrated;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fephym0_led_link>,
+ <&fephym0_led_spd>;
+ resets = <&cru SRST_MACPHY>;
+ };
+ };
+
+ gmac0_stmmac_axi_setup: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <8>;
+ snps,wr_osr_lmt = <4>;
+ };
+
+ gmac0_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ queue0 {};
+ };
+
+ gmac0_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+ queue0 {};
+ };
+ };
+
+ gmac1: ethernet@ffbe0000 {
+ compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0xffbe0000 0x0 0x10000>;
+ clocks = <&cru CLK_GMAC1_SRC_VPU>,
+ <&cru CLK_GMAC1_RMII_VPU>,
+ <&cru PCLK_MAC_VPU>,
+ <&cru ACLK_MAC_VPU>;
+ clock-names = "stmmaceth",
+ "clk_mac_ref",
+ "pclk_mac",
+ "aclk_mac";
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ resets = <&cru SRST_A_MAC>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&vpu_grf>;
+ snps,axi-config = <&gmac1_stmmac_axi_setup>;
+ snps,mixed-burst;
+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
+ snps,tso;
+ status = "disabled";
+
+ mdio1: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ gmac1_stmmac_axi_setup: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <8>;
+ snps,wr_osr_lmt = <4>;
+ };
+
+ gmac1_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ queue0 {};
+ };
+
+ gmac1_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+ queue0 {};
+ };
+ };
+
sdhci: mmc@ffbf0000 {
compatible = "rockchip,rk3528-dwcmshc",
"rockchip,rk3588-dwcmshc";

171
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@ -0,0 +1,171 @@
From 7d086f78fe09fb94eb3b2e12436f2feed21d9c1e Mon Sep 17 00:00:00 2001
From: Heiko Stuebner <heiko@sntech.de>
Date: Mon, 19 May 2025 00:04:46 +0200
Subject: [PATCH] arm64: dts: rockchip: move rk3528 pinctrl node outside the
soc node
The non-mmio pinctrl node is not supposed to be inside the soc simple-bus
as dtc points out:
../arch/arm64/boot/dts/rockchip/rk3528.dtsi:870.20-936.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property
Move the pinctrl node outside and adapt the indentation.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250518220449.2722673-5-heiko@sntech.de
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 136 +++++++++++------------
1 file changed, 68 insertions(+), 68 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -111,6 +111,74 @@
};
};
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3528-pinctrl";
+ rockchip,grf = <&ioc_grf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@ff610000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff610000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@ffaf0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffaf0000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@ffb00000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb00000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@ffb10000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb10000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@ffb20000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb20000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@@ -882,74 +950,6 @@
#dma-cells = <1>;
arm,pl330-periph-burst;
};
-
- pinctrl: pinctrl {
- compatible = "rockchip,rk3528-pinctrl";
- rockchip,grf = <&ioc_grf>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio0: gpio@ff610000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff610000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 0 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@ffaf0000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xffaf0000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 32 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@ffb00000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xffb00000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 64 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@ffb10000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xffb10000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 96 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@ffb20000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xffb20000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 128 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
};
};

51
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@ -0,0 +1,51 @@
From 2783335329e5762deb0dc5b6d634225d8613af16 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Tue, 20 May 2025 18:01:02 +0800
Subject: [PATCH] arm64: dts: rockchip: Add spi nodes for RK3528
There are 2 SPI controllers on the RK3528 SoC, describe it.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20250520100102.1226725-3-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 28 ++++++++++++++++++++++++
1 file changed, 28 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -455,6 +455,34 @@
reg = <0x0 0xff540000 0x0 0x40000>;
};
+ spi0: spi@ff9c0000 {
+ compatible = "rockchip,rk3528-spi",
+ "rockchip,rk3066-spi";
+ reg = <0x0 0xff9c0000 0x0 0x1000>;
+ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
+ clock-names = "spiclk", "apb_pclk";
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 25>, <&dmac 24>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@ff9d0000 {
+ compatible = "rockchip,rk3528-spi",
+ "rockchip,rk3066-spi";
+ reg = <0x0 0xff9d0000 0x0 0x1000>;
+ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
+ clock-names = "spiclk", "apb_pclk";
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 31>, <&dmac 30>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
uart0: serial@ff9f0000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xff9f0000 0x0 0x100>;

94
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@ -0,0 +1,94 @@
From 654df8e74dbc19ba0625051079e6889e6999d16e Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 18 May 2025 22:06:51 +0000
Subject: [PATCH] arm64: dts: rockchip: Add power controller for RK3528
Add power-domain nodes for the power controller on RK3528.
Only PD_GPU can fully be powered down. PD_RKVDEC, PD_RKVENC, PD_VO and
PD_VPU are idle only power domains used by miscellaneous devices.
Because multiple of the miscellaneous device types currently complain
about the use of a power-domains prop, only PD_GPU is enabled.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250518220707.669515-5-jonas@kwiboo.se
[changed to using numeric values, until the next merge-window]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 64 ++++++++++++++++++++++++
1 file changed, 64 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -455,6 +455,70 @@
reg = <0x0 0xff540000 0x0 0x40000>;
};
+ pmu: power-management@ff600000 {
+ compatible = "rockchip,rk3528-pmu", "syscon", "simple-mfd";
+ reg = <0x0 0xff600000 0x0 0x2000>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3528-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* These power domains are grouped by VD_GPU */
+ power-domain@4 {
+ reg = <4>;
+ clocks = <&cru ACLK_GPU_MALI>,
+ <&cru PCLK_GPU_ROOT>;
+ pm_qos = <&qos_gpu_m0>,
+ <&qos_gpu_m1>;
+ #power-domain-cells = <0>;
+ };
+
+ /* These power domains are grouped by VD_LOGIC */
+ power-domain@5 {
+ reg = <5>;
+ pm_qos = <&qos_rkvdec>;
+ #power-domain-cells = <0>;
+ status = "disabled";
+ };
+ power-domain@6 {
+ reg = <6>;
+ pm_qos = <&qos_rkvenc>;
+ #power-domain-cells = <0>;
+ status = "disabled";
+ };
+ power-domain@7 {
+ reg = <7>;
+ pm_qos = <&qos_gmac0>,
+ <&qos_hdcp>,
+ <&qos_jpegdec>,
+ <&qos_rga2_m0ro>,
+ <&qos_rga2_m0wo>,
+ <&qos_sdmmc0>,
+ <&qos_usb2host>,
+ <&qos_vdpp>,
+ <&qos_vop>;
+ #power-domain-cells = <0>;
+ status = "disabled";
+ };
+ power-domain@8 {
+ reg = <8>;
+ pm_qos = <&qos_emmc>,
+ <&qos_fspi>,
+ <&qos_gmac1>,
+ <&qos_pcie>,
+ <&qos_sdio0>,
+ <&qos_sdio1>,
+ <&qos_tsp>,
+ <&qos_usb3otg>,
+ <&qos_vpu>;
+ #power-domain-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
spi0: spi@ff9c0000 {
compatible = "rockchip,rk3528-spi",
"rockchip,rk3066-spi";

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@ -0,0 +1,88 @@
From 06601cc45b5ba0c3bcd371b9c499d9fe5dabd11d Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 18 May 2025 22:54:12 +0000
Subject: [PATCH] arm64: dts: rockchip: Add GPU node for RK3528
Add a GPU node and a opp-table for the Mali-450 MP2 in the RK3528 SoC.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250518225418.682182-3-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 58 ++++++++++++++++++++++++
1 file changed, 58 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -111,6 +111,36 @@
};
};
+ gpu_opp_table: opp-table-gpu {
+ compatible = "operating-points-v2";
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <875000 875000 1000000>;
+ opp-suspend;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <875000 875000 1000000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <875000 875000 1000000>;
+ };
+
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <900000 900000 1000000>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <950000 950000 1000000>;
+ };
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3528-pinctrl";
rockchip,grf = <&ioc_grf>;
@@ -519,6 +549,34 @@
};
};
+ gpu: gpu@ff700000 {
+ compatible = "rockchip,rk3528-mali", "arm,mali-450";
+ reg = <0x0 0xff700000 0x0 0x40000>;
+ assigned-clocks = <&cru ACLK_GPU_MALI>,
+ <&scmi_clk SCMI_CLK_GPU>;
+ assigned-clock-rates = <297000000>, <300000000>;
+ clocks = <&cru ACLK_GPU_MALI>, <&scmi_clk SCMI_CLK_GPU>;
+ clock-names = "bus", "core";
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1";
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&power 4>;
+ resets = <&cru SRST_A_GPU>;
+ status = "disabled";
+ };
+
spi0: spi@ff9c0000 {
compatible = "rockchip,rk3528-spi",
"rockchip,rk3066-spi";

125
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@ -0,0 +1,125 @@
From f2792bf1c7a54ef23fb3a84286b66f427bfc4853 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sat, 21 Jun 2025 11:38:57 +0000
Subject: [PATCH] arm64: dts: rockchip: Fix pinctrl node names for RK3528
Following warnings can be observed with CHECK_DTBS=y for the RK3528:
rk3528-pinctrl.dtsi:101.36-105.5: Warning (node_name_chars_strict):
/pinctrl/fephy/fephym0-led_dpx: Character '_' not recommended in node name
rk3528-pinctrl.dtsi:108.38-112.5: Warning (node_name_chars_strict):
/pinctrl/fephy/fephym0-led_link: Character '_' not recommended in node name
rk3528-pinctrl.dtsi:115.36-119.5: Warning (node_name_chars_strict):
/pinctrl/fephy/fephym0-led_spd: Character '_' not recommended in node name
rk3528-pinctrl.dtsi:122.36-126.5: Warning (node_name_chars_strict):
/pinctrl/fephy/fephym1-led_dpx: Character '_' not recommended in node name
rk3528-pinctrl.dtsi:129.38-133.5: Warning (node_name_chars_strict):
/pinctrl/fephy/fephym1-led_link: Character '_' not recommended in node name
rk3528-pinctrl.dtsi:136.36-140.5: Warning (node_name_chars_strict):
/pinctrl/fephy/fephym1-led_spd: Character '_' not recommended in node name
rk3528-pinctrl.dtsi:782.32-790.5: Warning (node_name_chars_strict):
/pinctrl/rgmii/rgmii-rx_bus2: Character '_' not recommended in node name
rk3528-pinctrl.dtsi:793.32-801.5: Warning (node_name_chars_strict):
/pinctrl/rgmii/rgmii-tx_bus2: Character '_' not recommended in node name
rk3528-pinctrl.dtsi:804.36-810.5: Warning (node_name_chars_strict):
/pinctrl/rgmii/rgmii-rgmii_clk: Character '_' not recommended in node name
rk3528-pinctrl.dtsi:813.36-823.5: Warning (node_name_chars_strict):
/pinctrl/rgmii/rgmii-rgmii_bus: Character '_' not recommended in node name
Rename the affected nodes to fix these warnings.
Fixes: a31fad19ae39 ("arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250621113859.2146400-1-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
.../boot/dts/rockchip/rk3528-pinctrl.dtsi | 20 +++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi
@@ -98,42 +98,42 @@
fephy {
/omit-if-no-ref/
- fephym0_led_dpx: fephym0-led_dpx {
+ fephym0_led_dpx: fephym0-led-dpx {
rockchip,pins =
/* fephy_led_dpx_m0 */
<4 RK_PB5 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
- fephym0_led_link: fephym0-led_link {
+ fephym0_led_link: fephym0-led-link {
rockchip,pins =
/* fephy_led_link_m0 */
<4 RK_PC0 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
- fephym0_led_spd: fephym0-led_spd {
+ fephym0_led_spd: fephym0-led-spd {
rockchip,pins =
/* fephy_led_spd_m0 */
<4 RK_PB7 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
- fephym1_led_dpx: fephym1-led_dpx {
+ fephym1_led_dpx: fephym1-led-dpx {
rockchip,pins =
/* fephy_led_dpx_m1 */
<2 RK_PA4 5 &pcfg_pull_none>;
};
/omit-if-no-ref/
- fephym1_led_link: fephym1-led_link {
+ fephym1_led_link: fephym1-led-link {
rockchip,pins =
/* fephy_led_link_m1 */
<2 RK_PA6 5 &pcfg_pull_none>;
};
/omit-if-no-ref/
- fephym1_led_spd: fephym1-led_spd {
+ fephym1_led_spd: fephym1-led-spd {
rockchip,pins =
/* fephy_led_spd_m1 */
<2 RK_PA5 5 &pcfg_pull_none>;
@@ -779,7 +779,7 @@
};
/omit-if-no-ref/
- rgmii_rx_bus2: rgmii-rx_bus2 {
+ rgmii_rx_bus2: rgmii-rx-bus2 {
rockchip,pins =
/* rgmii_rxd0 */
<3 RK_PA3 2 &pcfg_pull_none>,
@@ -790,7 +790,7 @@
};
/omit-if-no-ref/
- rgmii_tx_bus2: rgmii-tx_bus2 {
+ rgmii_tx_bus2: rgmii-tx-bus2 {
rockchip,pins =
/* rgmii_txd0 */
<3 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
@@ -801,7 +801,7 @@
};
/omit-if-no-ref/
- rgmii_rgmii_clk: rgmii-rgmii_clk {
+ rgmii_rgmii_clk: rgmii-rgmii-clk {
rockchip,pins =
/* rgmii_rxclk */
<3 RK_PA5 2 &pcfg_pull_none>,
@@ -810,7 +810,7 @@
};
/omit-if-no-ref/
- rgmii_rgmii_bus: rgmii-rgmii_bus {
+ rgmii_rgmii_bus: rgmii-rgmii-bus {
rockchip,pins =
/* rgmii_rxd2 */
<3 RK_PA7 2 &pcfg_pull_none>,

106
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@ -0,0 +1,106 @@
From ae019f0bdfbef3e0671e7b954321e92fc24c7e54 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 9 Jul 2025 21:08:28 +0000
Subject: [PATCH] arm64: dts: rockchip: Fix UART DMA support for RK3528
Trying to use UART2 DMA for Bluetooth on ArmSoM Sige1 result in tx
timeout when using dma-names = "tx", "rx" as required by the dt-binding:
Bluetooth: hci0: command 0x0c03 tx timeout
Bluetooth: hci0: BCM: Reset failed (-110)
Change the dmas order to fix UART DMA support on RK3528.
With this fixed Bluetooth can be loaded using DMA on ArmSoM Sige1:
Bluetooth: hci0: BCM: chip id 159
Bluetooth: hci0: BCM: features 0x0f
Bluetooth: hci0: BCM4362A2
Bluetooth: hci0: BCM4362A2 (000.017.017) build 0000
Bluetooth: hci0: BCM4362A2 'brcm/BCM4362A2.hcd' Patch
Bluetooth: hci0: BCM: features 0x0f
Bluetooth: hci0: BCM43752A2 UART 37.4MHz Ampak AP6398 sLNA iLNA CL1 [Version: 1091.1173]
Bluetooth: hci0: BCM4362A2 (000.017.017) build 1173
Fixes: ab6fcb58aedf ("arm64: dts: rockchip: Add UART DMA support for RK3528")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250709210831.3170458-1-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -611,7 +611,7 @@
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac 8>, <&dmac 9>;
+ dmas = <&dmac 9>, <&dmac 8>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -623,7 +623,7 @@
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac 10>, <&dmac 11>;
+ dmas = <&dmac 11>, <&dmac 10>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -635,7 +635,7 @@
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac 12>, <&dmac 13>;
+ dmas = <&dmac 13>, <&dmac 12>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -647,7 +647,7 @@
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac 14>, <&dmac 15>;
+ dmas = <&dmac 15>, <&dmac 14>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -659,7 +659,7 @@
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac 16>, <&dmac 17>;
+ dmas = <&dmac 17>, <&dmac 16>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -671,7 +671,7 @@
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac 18>, <&dmac 19>;
+ dmas = <&dmac 19>, <&dmac 18>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -683,7 +683,7 @@
clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac 20>, <&dmac 21>;
+ dmas = <&dmac 21>, <&dmac 20>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -695,7 +695,7 @@
clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dmac 22>, <&dmac 23>;
+ dmas = <&dmac 23>, <&dmac 22>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";

85
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@ -0,0 +1,85 @@
From 1bce3444df79910512587a1f18022c396e9430b5 Mon Sep 17 00:00:00 2001
From: Heiko Stuebner <heiko@sntech.de>
Date: Fri, 20 Jun 2025 22:17:15 +0200
Subject: [PATCH] arm64: dts: rockchip: convert rk3528 power-domains to
dt-binding constants
Now that the binding head has been merged, convert the power-domain ids
back to these constants for easier handling.
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250620201715.1572609-1-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rockchip,rk3528-cru.h>
+#include <dt-bindings/power/rockchip,rk3528-power.h>
#include <dt-bindings/reset/rockchip,rk3528-cru.h>
/ {
@@ -496,8 +497,8 @@
#size-cells = <0>;
/* These power domains are grouped by VD_GPU */
- power-domain@4 {
- reg = <4>;
+ power-domain@RK3528_PD_GPU {
+ reg = <RK3528_PD_GPU>;
clocks = <&cru ACLK_GPU_MALI>,
<&cru PCLK_GPU_ROOT>;
pm_qos = <&qos_gpu_m0>,
@@ -506,20 +507,20 @@
};
/* These power domains are grouped by VD_LOGIC */
- power-domain@5 {
- reg = <5>;
+ power-domain@RK3528_PD_RKVDEC {
+ reg = <RK3528_PD_RKVDEC>;
pm_qos = <&qos_rkvdec>;
#power-domain-cells = <0>;
status = "disabled";
};
- power-domain@6 {
- reg = <6>;
+ power-domain@RK3528_PD_RKVENC {
+ reg = <RK3528_PD_RKVENC>;
pm_qos = <&qos_rkvenc>;
#power-domain-cells = <0>;
status = "disabled";
};
- power-domain@7 {
- reg = <7>;
+ power-domain@RK3528_PD_VO {
+ reg = <RK3528_PD_VO>;
pm_qos = <&qos_gmac0>,
<&qos_hdcp>,
<&qos_jpegdec>,
@@ -532,8 +533,8 @@
#power-domain-cells = <0>;
status = "disabled";
};
- power-domain@8 {
- reg = <8>;
+ power-domain@RK3528_PD_VPU {
+ reg = <RK3528_PD_VPU>;
pm_qos = <&qos_emmc>,
<&qos_fspi>,
<&qos_gmac1>,
@@ -572,7 +573,7 @@
"pp1",
"ppmmu1";
operating-points-v2 = <&gpu_opp_table>;
- power-domains = <&power 4>;
+ power-domains = <&power RK3528_PD_GPU>;
resets = <&cru SRST_A_GPU>;
status = "disabled";
};

55
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@ -0,0 +1,55 @@
From 70bb21cbc8c704c664b5d3ea417f3e35376fc229 Mon Sep 17 00:00:00 2001
From: Yao Zi <ziyao@disroot.org>
Date: Mon, 28 Jul 2025 10:29:48 +0000
Subject: [PATCH] arm64: dts: rockchip: Add naneng-combphy for RK3528
Rockchip RK3528 ships a naneng-combphy that is shared by PCIe and USB
3.0 controllers. Describe it and the pipe-phy grf which it depends on.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20250728102947.38984-8-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -433,6 +433,11 @@
reg = <0x0 0xff340000 0x0 0x8000>;
};
+ pipe_phy_grf: syscon@ff348000 {
+ compatible = "rockchip,rk3528-pipe-phy-grf", "syscon";
+ reg = <0x0 0xff348000 0x0 0x8000>;
+ };
+
vo_grf: syscon@ff360000 {
compatible = "rockchip,rk3528-vo-grf", "syscon";
reg = <0x0 0xff360000 0x0 0x10000>;
@@ -1101,6 +1106,25 @@
#dma-cells = <1>;
arm,pl330-periph-burst;
};
+
+ combphy: phy@ffdc0000 {
+ compatible = "rockchip,rk3528-naneng-combphy";
+ reg = <0x0 0xffdc0000 0x0 0x10000>;
+ assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>;
+ assigned-clock-rates = <100000000>;
+ clocks = <&cru CLK_REF_PCIE_INNER_PHY>,
+ <&cru PCLK_PCIE_PHY>,
+ <&cru PCLK_PIPE_GRF>;
+ clock-names = "ref", "apb", "pipe";
+ power-domains = <&power RK3528_PD_VPU>;
+ resets = <&cru SRST_PCIE_PIPE_PHY>,
+ <&cru SRST_P_PCIE_PHY>;
+ reset-names = "phy", "apb";
+ #phy-cells = <1>;
+ rockchip,pipe-grf = <&vpu_grf>;
+ rockchip,pipe-phy-grf = <&pipe_phy_grf>;
+ status = "disabled";
+ };
};
};

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@ -0,0 +1,261 @@
From 178879625f0f10ff708728087d91a5fe79990ce2 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Thu, 21 Aug 2025 21:18:41 +0000
Subject: [PATCH] arm64: dts: rockchip: Enable more power domains for RK3528
Describe device power-domains and enable the PD_RKVENC, PD_VO and PD_VPU
power-domains on RK3528.
The PD_RKVDEC is used by RKVDEC and DDRPHY CRU, and is kept disabled to
prevent a full system reset trying to read the rate of the SCMI_CLK_DDR
clock.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250821211843.3051349-2-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 30 +++++++++++++++++++++---
1 file changed, 27 insertions(+), 3 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -171,6 +171,7 @@
gpio-ranges = <&pinctrl 0 32 32>;
interrupt-controller;
#interrupt-cells = <2>;
+ power-domains = <&power RK3528_PD_VPU>;
};
gpio2: gpio@ffb00000 {
@@ -183,6 +184,7 @@
gpio-ranges = <&pinctrl 0 64 32>;
interrupt-controller;
#interrupt-cells = <2>;
+ power-domains = <&power RK3528_PD_VO>;
};
gpio3: gpio@ffb10000 {
@@ -195,6 +197,7 @@
gpio-ranges = <&pinctrl 0 96 32>;
interrupt-controller;
#interrupt-cells = <2>;
+ power-domains = <&power RK3528_PD_VPU>;
};
gpio4: gpio@ffb20000 {
@@ -207,6 +210,7 @@
gpio-ranges = <&pinctrl 0 128 32>;
interrupt-controller;
#interrupt-cells = <2>;
+ power-domains = <&power RK3528_PD_RKVENC>;
};
};
@@ -522,7 +526,6 @@
reg = <RK3528_PD_RKVENC>;
pm_qos = <&qos_rkvenc>;
#power-domain-cells = <0>;
- status = "disabled";
};
power-domain@RK3528_PD_VO {
reg = <RK3528_PD_VO>;
@@ -536,7 +539,6 @@
<&qos_vdpp>,
<&qos_vop>;
#power-domain-cells = <0>;
- status = "disabled";
};
power-domain@RK3528_PD_VPU {
reg = <RK3528_PD_VPU>;
@@ -550,7 +552,6 @@
<&qos_usb3otg>,
<&qos_vpu>;
#power-domain-cells = <0>;
- status = "disabled";
};
};
};
@@ -592,6 +593,7 @@
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 25>, <&dmac 24>;
dma-names = "tx", "rx";
+ power-domains = <&power RK3528_PD_RKVENC>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -606,6 +608,7 @@
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 31>, <&dmac 30>;
dma-names = "tx", "rx";
+ power-domains = <&power RK3528_PD_VPU>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -630,6 +633,7 @@
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 11>, <&dmac 10>;
+ power-domains = <&power RK3528_PD_RKVENC>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -642,6 +646,7 @@
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 13>, <&dmac 12>;
+ power-domains = <&power RK3528_PD_VPU>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -654,6 +659,7 @@
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 15>, <&dmac 14>;
+ power-domains = <&power RK3528_PD_RKVENC>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -666,6 +672,7 @@
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 17>, <&dmac 16>;
+ power-domains = <&power RK3528_PD_VO>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -678,6 +685,7 @@
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 19>, <&dmac 18>;
+ power-domains = <&power RK3528_PD_VPU>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -690,6 +698,7 @@
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 21>, <&dmac 20>;
+ power-domains = <&power RK3528_PD_VPU>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -702,6 +711,7 @@
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 23>, <&dmac 22>;
+ power-domains = <&power RK3528_PD_VPU>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -714,6 +724,7 @@
clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3528_PD_RKVENC>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -726,6 +737,7 @@
clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3528_PD_RKVENC>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -752,6 +764,7 @@
clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3528_PD_VPU>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -766,6 +779,7 @@
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4_xfer>;
+ power-domains = <&power RK3528_PD_VO>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -778,6 +792,7 @@
clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3528_PD_VPU>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -790,6 +805,7 @@
clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3528_PD_VPU>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -804,6 +820,7 @@
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c7_xfer>;
+ power-domains = <&power RK3528_PD_VO>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -895,6 +912,7 @@
clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3528_PD_VPU>;
resets = <&cru SRST_P_SARADC>;
reset-names = "saradc-apb";
#io-channel-cells = <1>;
@@ -915,6 +933,7 @@
interrupt-names = "macirq", "eth_wake_irq";
phy-handle = <&rmii0_phy>;
phy-mode = "rmii";
+ power-domains = <&power RK3528_PD_VO>;
resets = <&cru SRST_A_MAC_VO>;
reset-names = "stmmaceth";
rockchip,grf = <&vo_grf>;
@@ -973,6 +992,7 @@
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
+ power-domains = <&power RK3528_PD_VPU>;
resets = <&cru SRST_A_MAC>;
reset-names = "stmmaceth";
rockchip,grf = <&vpu_grf>;
@@ -1023,6 +1043,7 @@
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
<&emmc_strb>;
+ power-domains = <&power RK3528_PD_VPU>;
resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
<&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
<&cru SRST_T_EMMC>;
@@ -1044,6 +1065,7 @@
max-frequency = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>;
+ power-domains = <&power RK3528_PD_VPU>;
resets = <&cru SRST_H_SDIO0>;
reset-names = "reset";
status = "disabled";
@@ -1063,6 +1085,7 @@
max-frequency = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>;
+ power-domains = <&power RK3528_PD_VPU>;
resets = <&cru SRST_H_SDIO1>;
reset-names = "reset";
status = "disabled";
@@ -1083,6 +1106,7 @@
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>,
<&sdmmc_det>;
+ power-domains = <&power RK3528_PD_VO>;
resets = <&cru SRST_H_SDMMC0>;
reset-names = "reset";
rockchip,default-sample-phase = <90>;

98
target/linux/rockchip/patches-6.12/070-25-v6.18-arm64-dts-rockchip-Add-rk3528-CPU-frequency-scaling.patch Normal file
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@ -0,0 +1,98 @@
From 42bbc32c7e9e974ae4eb830ae1381cb016133e5c Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Fri, 1 Aug 2025 16:00:25 +0800
Subject: [PATCH] arm64: dts: rockchip: Add rk3528 CPU frequency scaling
support
By default, the CPUs on RK3528 operates at 1.5GHz. Add CPU frequency and
voltage mapping to the device tree to enable dynamic scaling via cpufreq.
The OPP values come from downstream kernel[1], using a voltage close to
the actual frequency. Frequencies below 1.2GHz have been removed due to
the same voltage.
[1] https://github.com/rockchip-linux/kernel/blob/develop-5.10/arch/arm64/boot/dts/rockchip/rk3528.dtsi
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20250801080025.558935-2-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 39 ++++++++++++++++++++++++
1 file changed, 39 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -70,6 +70,7 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_clk SCMI_CLK_CPU>;
+ operating-points-v2 = <&cpu_opp_table>;
};
cpu1: cpu@1 {
@@ -78,6 +79,7 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_clk SCMI_CLK_CPU>;
+ operating-points-v2 = <&cpu_opp_table>;
};
cpu2: cpu@2 {
@@ -86,6 +88,7 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_clk SCMI_CLK_CPU>;
+ operating-points-v2 = <&cpu_opp_table>;
};
cpu3: cpu@3 {
@@ -94,6 +97,7 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_clk SCMI_CLK_CPU>;
+ operating-points-v2 = <&cpu_opp_table>;
};
};
@@ -112,6 +116,41 @@
};
};
+ cpu_opp_table: opp-table-cpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <875000 875000 1100000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <925000 925000 1100000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <975000 975000 1100000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1037500 1037500 1100000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <1100000 1100000 1100000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
gpu_opp_table: opp-table-gpu {
compatible = "operating-points-v2";

92
target/linux/rockchip/patches-6.12/070-26-v6.18-arm64-dts-rockchip-Add-PCIe-Gen2x1-controller-for-RK3528.patch Normal file
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@ -0,0 +1,92 @@
From 263fac6b09b42a1b077c21354370d38758237ab0 Mon Sep 17 00:00:00 2001
From: Yao Zi <ziyao@disroot.org>
Date: Thu, 18 Sep 2025 15:30:56 +0000
Subject: [PATCH] arm64: dts: rockchip: Add PCIe Gen2x1 controller for RK3528
Describes the PCIe Gen2x1 controller integrated in RK3528 SoC. The SoC
doesn't provide a separate MSI controller, thus the one integrated in
designware PCIe IP must be used.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://patch.msgid.link/20250918153057.56023-3-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 56 +++++++++++++++++++++++++++++++-
1 file changed, 55 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rockchip,rk3528-cru.h>
#include <dt-bindings/power/rockchip,rk3528-power.h>
@@ -294,10 +295,63 @@
soc {
compatible = "simple-bus";
- ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
+ ranges = <0x0 0xfc000000 0x0 0xfc000000 0x0 0x44000000>;
#address-cells = <2>;
#size-cells = <2>;
+ pcie: pcie@fe000000 {
+ compatible = "rockchip,rk3528-pcie",
+ "rockchip,rk3568-pcie";
+ reg = <0x0 0xfe000000 0x0 0x400000>,
+ <0x0 0xfe4f0000 0x0 0x010000>,
+ <0x0 0xfc000000 0x0 0x100000>;
+ reg-names = "dbi", "apb", "config";
+ bus-range = <0x0 0xff>;
+ clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>,
+ <&cru HCLK_PCIE_DBI>, <&cru PCLK_PCIE>,
+ <&cru CLK_PCIE_AUX>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux";
+ device_type = "pci";
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err",
+ "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ linux,pci-domain = <0>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+ phys = <&combphy PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3528_PD_VPU>;
+ ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x00100000>,
+ <0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x01e00000>,
+ <0x03000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>;
+ resets = <&cru SRST_PCIE_POWER_UP>, <&cru SRST_P_PCIE>;
+ reset-names = "pwr", "pipe";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
gic: interrupt-controller@fed01000 {
compatible = "arm,gic-400";
reg = <0x0 0xfed01000 0 0x1000>,