eMMC part THGBMNG5D1LBAIT (Toshiba 4GB) is taking long time for
the secure trim.This leads to erase timeout. Manufacturer ID based
quirk is added for the specific part to use trim instead of secure
trim for block erase.
without this change we can see the error erase timeout and erase failed.
error:
MMC erase: dev # 0, block # 6690, count 2047 ... sdhci_send_command:
MMC: 0 busy timeout increasing to: 2000 ms.
sdhci_send_command: MMC: 0 busy timeout increasing to: 4000 ms.
timeout.
mmc erase failed
-1 blocks erased: ERROR
Change-Id: I1126690400b274bb4735750584d7fb4b105e6618
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This change will handle masking of DAT inhibit bit of
present state register. This status bit is genarated if
either the DAT Line Active or Read Transfer Active is set to
1. If this bit is 0, it indicates the host controller can issue
the next command.
Commands with busy signal belong to Command Inhibit(DAT).
e.g (R1b, R5b type).
Changing from 1 to 0 generates a transfer complete interrupt
in normal interrupt status register.
If this bit value is 1: Cannot issue command which uses DAT line.
If this bit value is 0: Can issue command which uses DAT line.
This change is masking SDHCI_DATA_INHIBIT bit only if card is in
busy state.
Without this change we can get the erase timeout error.
error:
MMC erase: dev # 0, block # 27682, count 16383 ...
sdhci_send_command: MMC: 0 busy timeout increasing to: 2000 ms.
Change-Id: I0612e576c09a7fd077bed1a1ee717afcddfa7e87
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Moved Aquantia, QCA8033, QCA8075 and QCA8081
PHY configs to defconfig.
For tiny u-boot variant, except QCA8075 all
other PHYs are disabled.
Change-Id: Iaafa848bf7d578bfa3bcdaf0cfcb815ecfef067f
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Some spi nand flash uses single byte read id(9FH) command,
for those devices the sequence is
byte1 byte2 byte3 byte4
9FH MID DID DID
some other spi nand flashes uses two byte read id(9F 00H) command
for those devices the sequence is
byte1 byte2 byte3 byte4
9FH A7-A0 MID DID
The first byte is the actual command and the second byte is a dummy byte.
For devices which uses new sequence, we need to pass
appropriate read id command with dummy byte.
Change-Id: Idf2e8740f8341596cd8f58d22d5e33a4b4972a31
Signed-off-by: Antony Arun T <antothom@codeaurora.org>
This change will clear the divider value while doing deinit of
SD devices. In-order to clear the divider value we have to write
into register GCC_SDCC1_MISC.
Writing 0x0 to this register will clear the divider value which is
set, while doing initialization got SD devices.
Without this change, while kernel bootup we can see the below error.
error:
[3.529917] mmc0: Skipping voltage switch
[4.131741] mmc0: error -110 whilst initialising SD card.
Change-Id: Ifeca94ae09532a4b506e645cc9254e438179c886
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
This change adds drive-strength property for I2C GPIOs and
modify config_i2c_gpio function to get the drvstr value from dts.
Change-Id: Ieece9e2f9d6abc115a50d87bc512004d3efcad0f
Signed-off-by: Pavithra Palanisamy <pavip@codeaurora.org>
This change is a workaround for Micron eMMC card. As per the card
extended CSD register value, the minimum size of a write protect
region is 0x8000 blocks (16MB). So the user should give start address
and size to align with 0x8000. But this eMMC part actually does
protect 32MB of memory.
We changing the minimum write protect region size from 0x8000 to
0x10000 for Micron eMMC card.
Change-Id: Id53c337374dfba8adb6bd550826337d8ecfe17f3
Signed-off-by: Vinoth Gnanasekaran <vgnana@codeaurora.org>
The Device will accept the requested number of data blocks, terminate
the transaction and return to transfer state. Stop command is not
required at the end of this type of multiple blocks write unless
terminated with an error. This change will send the
STOP_TRANIMISSION command if the command failed.
Change-Id: I9bd419ab8931d80a4a2eeba9f5bd42222257a824
Signed-off-by: Vinoth Gnanasekaran <vgnana@codeaurora.org>
The malibu phy stucks if the continuous tftp, ping and reboot tests in the
long run. Added the Malibu phy serdes and uniphy calibration for PSGMII mode.
Change-Id: Ie2e0dc363689fff69011560994b37adf6da76a17
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
During serial init after relocation, if TX FIFO is
not empty, clock init on-the-fly causes baudrate
flucutation resulting in TX data corruption and
outputs as garbage data on the console.
This patch fixes this by waiting until TX FIFO
gets flushed before serial initialization starts.
Change-Id: I487c73fbfb4fdb80b20d8beb8daa111ee9bae34e
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
This patch checks for the errors during the fifo write itself
like in qca_pio_read function. Previously, error was checked
only after the total xfer_size is written to the fifo and
errors during the fifo write operation were ignored.
Change-Id: I2a549b0032bfd774973773cc49b595c75682aac7
Signed-off-by: Balaji Prakash Jagadeesan <bjagadee@codeaurora.org>
We are allocating the dma descriptors,but they are not explicitly
freed. This change will free the dma descriptors after every transfer.
Change-Id: I0a851923ab4d2551215e29b34c7c31b85502fb3f
Signed-off-by: sameeruddin shaik <samesh@codeaurora.org>
This change modifies kstrtoint function to update
the result in destination buffer and return zero on success.
Change-Id: Ibdd9b36eed39d5e2ee3afc6f1609c1e35d5fb464
Signed-off-by: Pavithra Palanisamy <pavip@codeaurora.org>
Some cards are not working due to pcie reset.
So doing pcie reset with pcie reset gpio.
Change-Id: I0c631b116923b90bf94223d09e5662900a31244e
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Since set_sgmii_mode function does not return any value, changed its
functon type to void.
Change-Id: I4f098747ed2e562488cf97dc06dbb48a54b53fc3
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
